MC88915FN55R2 IDT, Integrated Device Technology Inc, MC88915FN55R2 Datasheet - Page 5

• Manufacturer Part Number: MC88915FN55R2
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915FN55R2

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 55MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 55MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915
LOW SKEW CMOS PLL CLOCK DRIVERS
Table 6. AC Electrical Characteristics (T
Table 7. Reset Timing Requirements
(Sync-Feedback)
1. These specifications are not tested, they are guaranteed by statistical characterization. See General AC Specification note 1.
2. Under equally loaded conditions, CL ≤ 50 pF (±2 pF), and at a fixed temperature and voltage.
3. With V
1. These reset specs are valid only when PLL_EN is LOW and the part is in Test mode (not in phase-lock)
(Q0,Q1,Q3,Q4,
(2X_Q Output)
(2X_Q Output)
(2X_Q Output)
t
t
SKEWall
t
t
t
t
RISE
t
C1 = 0.01µF.
t
Pulse Width
Pulse Width
Pulse Width
Pulse Width
(Reset - Q)
SKEWf
RISE
(Outputs)
(Q2 only)
t
Symbol
(Falling)
Q5,Q/2)
(Rising)
SKEWr
t
t
LOCK
PD
t
, t
PHL
, t
FALL
(1)
(1), (2)
CC
FALL
(1), (2)
(2)
t
REC
to SYNC
Symbol
t
(1)
(1)
(1)
(1)
fully powered-on and an output properly connected to the FEEDBACK pin. t
W
(1)
LOW
, RST
, RST
Rise and Fall Times, all Outputs Into a 50 pF, 500 Ω Load (Between
0.2 V
Rise and Fall Time, 2X_Q Output Into a 20 pF Load With Termination
specified in note 2 (Between 0.8 V and 2.0 V)
Output Pulse Width (Q0, Q1, Q3, Q4, Q5, Q/2 @V
Output Pulse Width (Q2 Output @ V
Output Pulse Width (2X_Q Output @ 1.5 V) (See General AC
Specification note 2)
Output Pulse Width (2X_Q Output @ V
SYNC input to feedback delay
(meas. @ SYNC0 or 1 and FEEDBACK input pins)
(See
Output-to-Output Skew Between Outputs Q0 - Q4, Q/2
(Rising Edges Only)
Output-to-Output Skew Between Outputs Q0 - Q4
(Falling Edges Only)
Output-to-Output Skew Between Outputs 2X_Q, Q/2, Q0 - Q4
Rising, Q5 Falling
Time Required to acquire
Signal is Received.
Propagation Delay, RST to Any Output (High-Low)
CC
General AC Specification Note 4.
and 0.8 V
Reset Recovery Time rising RST edge to falling SYNC edge
Minimum Pulse Width, RST input LOW
CC
)
(1)
(3)
A
Parameter
Phase-Lock from time SYNC Input
=0° C to +70° C, V
CC
/2)
CC
and
Parameter
/2)
Figure 4
CC
CC
5
for explanation)
/2)
= 5.0V ±5%, C
LOCK
L
= 50pF)
0.5t
0.5t
0.5t
0.5t
t
, Max. is with C1 = 0.1µF, t
(470 kΩ From RC1 to An. GND)
CYCLE
(470 kΩ From RC1 to An. V
CYCLE
CYCLE
CYCLE
CYCLE
+1.25
-1.05
Min
1.0
0.5
1.5
—
—
—
1
Outputs are running
= 1/Freq. at which the “Q”
Minimum
- 0.5
- 0.6
- 0.5
- 1.0
9.0
5.0
0.5t
0.5t
0.5t
0.5t
MC88915 REV 6 JULY 10, 2007
CYCLE
CYCLE
CYCLE
CYCLE
+3.25
-0.50
Max
13.5
500
750
750
2.5
1.6
10
LOCK
CC
+ 0.5
+ 0.6
+ 0.5
+ 1.0
)
Min. is with
Unit
ns
ns
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns