LMX2541SQ2060E/NOPB National Semiconductor, LMX2541SQ2060E/NOPB Datasheet - Page 35

• Manufacturer Part Number: LMX2541SQ2060E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQ2060E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.24GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.24GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQ2060E

the OSC_FREQ word is set correctly to have this work cor-
rectly.
The VCO also has an internal amplitude calibration algorithm
to optimize the phase noise which is also activated any time
the R0 register is programmed. The optimum internal settings
for this are temperature dependent. If the temperature is al-
lowed to drift too much without being re-calibrated, some
minor phase noise degradation could result. For applications
where this is an issue, the AC_TEMP_COMP word can be
used to sacrifice phase noise at room temperature in order to
improve the VCO phase noise over all temperatures. The
maximum allowable drift for continuous lock, ΔT
in the electrical specifications. For this part, a number of +125
C means the part will never lose lock if the part is operated
under recommended operating conditions.
1.7 PROGRAMMABLE VCO DIVIDER
The VCO divider can be programmed to any value from 2 to
63 as well as bypass mode if device is in full chip mode. In
external VCO mode or divider mode, all values except bypass
mode can be used for the VCO divider. The VCO divider is
not in the feedback path between the VCO and the PLL and
therefore has no impact on the PLL loop dynamics. After this
programmable divider is changed, it may be beneficial to re-
program the R0 register to recallibrate the VCO . The fre-
quency at the RFout pin is related to the VCO frequency and
divider value, VCO_DIV, as follows:
When this divider is enabled, there will be some far-out phase
noise contribution to the VCO noise. Also, it may be beneficial
for VCO phase noise to reprogram the R0 register to recali-
brate the VCO if the VCO_DIV value is changed from bypass
to divided, or vice-versa.
The duty cycle for this divider is always 50%, even for odd
divide values. Because of the architecture of this divider that
allows it to work to high frequencies and always have a 50%
duty cycle, there are a few extra considerations:
•
•
1.8 PROGRAMMABLE RF OUTPUT BUFFER
The output power at the RFout pin can be programmed to
various levels as well as on and off states. The output state
of this pin is controlled by the RFoutEN pin as well as the
RFOUT word. The RF output buffer can be disabled while still
keeping the PLL in lock. In addition to this, the actual output
power level of this pin can be adjusted using the VCOGAIN,
DIVGAIN, and OUTTERM programming words. The reader
should note that VCOGAIN controls the gain of the VCO
buffer, not the tuning constant in of the VCO.
1.9 POWERDOWN MODES
The LMX2541 can be powered up and down using the CE pin
or the POWERDOWN bit. When the device is powered down,
In divider only mode, there must be 5 clock cycles on the
ExtVCOin pin after the divide value is programmed in
order to cause the divide value to properly changed. It is
fine to use more than 5 clock cycles for this purpose.
For a divide of 4 or 5 ONLY, the R4 register needs to be
programmed one more time after the device is fully
programmed in order synchronize the divider. Failure to
do so will cause the VCO divider to divide by the wrong
value. Furthermore, if the VCO signal ever goes away, as
is the case when the part is powered down, it is necessary
to reprogram the R4 register again to re-synchronize the
divider. Furthermore, if the R0 register is ever
programmed in full chip mode, it is also necessary to
reprogram the R4 register.
f
RFout
= f
VCO
/ VCO_DIV
CL
, is stated
35
the programming and VCO calibration information is retained,
so it is not necessary to re-program the device when the de-
vice comes out of the powered down state (The one exception
is when the VCO_DIV value is 4 or 5, which has already been
discussed.). The following table shows how to use the bit and
pin.
The device can be programmed in the powerdown state.
However, the VCO frequency needs to be changed when the
device is powered up because the VCO calibration does not
run in the powerdown state. Also, the special programming
for VCO_DIV = 4 or 5 has to be done when the part is powered
up. In order for the CE pin to properly power the device down
when it is held low, the all registers in the device need to have
been programmed at least one time.
1.10 FASTLOCK
The LMX2541 includes the Fastlock ™ feature that can be
used to improve the lock times. When the frequency is
changed, a timeout counter is used to engage the fastlock for
a programmable amount of time. During the time that the de-
vice is in Fastlock, the FLout pin changes from high
impedance to low, thus switching in the external resistor R2-
pLF with R2_LF as well as changing the internal loop filter
values for R3_LF and R4_LF.
The following table shows the charge pump gain, loop filter
resistors, and FLout pin change between normal operation
and Fastlock.
Once the loop filter values and charge pump gain are known
for normal mode operation, they can be determined for fast-
lock operation as well. In normal operation, one can not use
the highest charge pump gain and still use fastlock because
there will be no larger current to switch in. If the resistors and
the charge pump current are done simultaneously, then the
phase margin can be preserved while increasing the loop
bandwidth by a factor of K as shown in the following table:
Loop Filter Resistor R3_LF
Loop Filter Resistor R4_LF
CE Pin
Charge Pump Gain
High
Low
Parameter
FLout Pin
POWERDOWN
Don't Care
Bit
0
1
Impedance
Operation
Normal
R3_LF
R4_LF
CPG
High
Powered Down
Powered Down
Device State
Powered Up
FL_R3_LF
FL_R4_LF
www.national.com
Fastlock
FL_CPG
Low
30073305