NBC12429AFAG ON Semiconductor, NBC12429AFAG Datasheet - Page 8

• Manufacturer Part Number: NBC12429AFAG
• Description: IC CLOCK SYNTH 25-400MHZ 32-LQFP
• Manufacturer: ON Semiconductor
• Type: PLL Clock Generatorr

Specifications of NBC12429AFAG

• Pll: Yes
• Input: Crystal
• Output: PECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 16 MHz crystal, this provides a
reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 9,
any crystal in the 10 MHz − 20 MHz range can be used,
Table 11.
400 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of this
loop divider is also applied to the phase detector.
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.
divider before being sent to the PECL output driver. This
output divider (N divider) is configured through either the
serial or the parallel interfaces and can provide one of four
division ratios (1, 2, 4, or 8). This divider extends the
performance of the part while providing a 50% duty cycle.
divider and is capable of driving a pair of transmission lines
terminated into 50 W to V
Table 8. AC CHARACTERISTICS
(Note 6)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
6. F
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used
t
t
t
DCO
t
s
h
pwMIN
r
, t
The internal oscillator uses the external quartz crystal as
The VCO within the PLL operates over a range of 200 to
The phase detector and the loop filter force the VCO
The output of the VCO is also passed through an output
The output driver is driven differentially from the output
Symbol
f
as a test clock in TEST_MODE 6.
OUT
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
/F
OUT
Setup Time
Hold Time
Minimum Pulse Width
Output Duty Cycle
Output Rise/Fall
outputs are terminated through a 50 W resistor to V
CC
− 2.0 V. The positive reference
Characteristic
(V
CC
S_CLOCK to S_LOAD
S_DATA to S_CLOCK
S_DATA to S_CLOCK
= 3.125 V to 5.25 V; T
FUNCTIONAL DESCRIPTION
M, N to P_LOAD
M, N to P_LOAD
http://onsemi.com
S_LOAD
P_LOAD
F
OUT
CC
A
8
= 0°C to 70°C (NBC12429), T
20%−80%
− 2.0 V.
for the output driver and the internal logic is separated from
the power supply for the PLL to minimize noise induced
jitter.
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held
LOW until sometime after power becomes valid. On the
LOW−to−HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH−to−LOW edge of the
S_LOAD input. See the programming section for more
information.
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
The configuration logic has two sections: serial and
The serial interface logic is implemented with a fourteen
The TEST output reflects various internal node values and
Condition
A
= −40°C to 85°C (NBC12429A))
47.5
Min
175
20
20
20
20
20
50
50
Max
52.5
425
Unit
ns
ns
ns
ps
%