CY2291F Cypress Semiconductor Corp, CY2291F Datasheet - Page 8

• Manufacturer Part Number: CY2291F
• Description: IC 3PLL EPROM CLOCK GEN 20-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2291F

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 66.6MHz, 90MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 66.6MHz/90MHz
• For Use With: CY3093 - SOCKET ADAPTER FTG FOR CY2291F428-1457 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1392

Switching Characteristics, Industrial 5.0V
Switching Characteristics, Industrial 3.3V
Document #: 38-07189 Rev. *D
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
1
3
4
5
6
7
8
9A
9B
9C
9D
10A
10B
1
3
4
5
Output Period
Output Duty
Cycle
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter
Clock Jitter
Clock Jitter
Clock Jitter
Lock Time for
CPLL
Lock Time for
UPLL and SPLL
Slew Limits
Output Period
Output Duty
Cycle
Rise Time
Fall Time
Output Disable
Time
Name
Name
[11]
[11]
[14]
[14]
[14]
[14]
Clock output range,
5V operation
Duty cycle for outputs, defined as t
f
Duty cycle for outputs, defined as t
f
Output clock rise time
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
12, 15]
Frequency transition rate
Peak-to-peak period jitter (t
clock period (f
Peak-to-peak period jitter (t
< f
Peak-to-peak period jitter
(16 MHz < f
Peak-to-peak period jitter
(f
Lock Time from Power Up
Lock Time from Power Up
CPU PLL Slew Limits
Clock output range, 3.3V
operation
Duty cycle for outputs, defined as t
f
Duty cycle for outputs, defined as t
f
Output clock rise time
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
OUT
OUT
OUT
OUT
OUT
OUT
> 66 MHZ
< 66 MHZ
> 66 MHZ
< 66 MHZ
> 50 MHz)
< 16 MHz)
OUT
OUT
< 50 MHz)
< 4 MHz)
[13]
[13]
Description
Description
[13]
[13]
9A
9B
CY2291I
CY2291FI
CY2291I
CY2291FI
CY2291I
CY2291FI
Max. – t
Max. – t
2
2
2
2
 t
 t
 t
 t
9A
9B
1
1
1
1
[12]
[12]
[12]
[12]
min.),% of
min.) (4 MHz
[3,
(66.6 MHz)
(90 MHz)
(80 MHz)
(60 MHz)
16.66
Min.
12.5
40%
45%
Min.
40%
45%
11.1
1.0
15
8
8
< 0.25
<0.25
<400
<250
50%
50%
Typ.
50%
50%
<0.5
<0.7
Typ.
<25
2.5
2.5
10
10
10
3
3
(76.923 kHz)
(76.923 kHz)
(76.923 kHz)
(76.923 kHz)
13000
13000
13000
13000
Max.
Max.
60%
55%
60%
55%
20.0
500
350
0.5
15
15
15
50
90
80
5
4
5
4
1
1
1
CY2291
Page 8 of 12
MHz/m
MHz
MHz
Unit
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%
s
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