MPC951FA Freescale Semiconductor, MPC951FA Datasheet

MPC951FA

Manufacturer Part Number

MPC951FA

Description

IC PLL CLOCK DRIVER 32-LQFP

Manufacturer

Freescale Semiconductor

Type

Clock Driver, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Datasheet

1.MPC951FAR2.pdf (12 pages)

Specifications of MPC951FA

Pll

Yes

Input

LVCMOS, LVTTL

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

3:9

Differential - Input:output

No/No

Frequency - Max

180MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

32-LQFP

Frequency-max

180MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MPC951FA

Manufacturer:

MOT

Quantity:

Company:

Meier Automation Equipment Co., Limited

Part Number:

MPC951FA

Manufacturer:

MOTOROLA/摩托罗拉

Quantity:

20 000

Current page: 1 of 12
Download datasheet (133Kb)

Low Voltage PLL Clock Driver

targeted for high performance clock tree designs. With output frequencies

of up to 180MHz and output skews of 375ps the MPC951 is ideal for the

most demanding clock tree designs. The devices employ a fully

differential PLL design to minimize cycle–to–cycle and long term jitter.

This parameter is of significant importance when the clock driver is

providing the reference clock for PLL’s on board today’s microprocessors

and ASiC’s. The devices offer 9 low skew outputs, the outputs are

configurable to support the clocking needs of the various high

performance microprocessors.

feedback input. These features allow for the MPC951 to be used as a

zero delay, low skew fanout buffer. In addition, the external feedback

allows for a wider variety of input–to–output frequency relationships. The

REF_SEL pin allows for the selection of an alternate LVCMOS input clock

to be used as a test clock or to provide the reference for the PLL from an

LVCMOS source.

compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50 transmission lines. Select

inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the PECL_CLK inputs are not used,

they can be left open. For series terminated 50

effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead LQFP package to provide the optimum combination of

board density and performance.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

06/00

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 2000

Fully Integrated PLL

Output Frequency up to 180MHz

Outputs Disable in High Impedance

Compatible with PowerPC , Intel and High Performance RISC

Microprocessors

LQFP Packaging

Output Frequency Configurable

The MPC951 is a 3.3V compatible, PLL based clock driver device

The MPC951 uses a differential PECL reference input and an external

The MPC951 is fully 3.3V compatible and require no external loop filter components. All inputs accept LVCMOS or LVTTL

100ps Typical Cycle–to–Cycle Jitter

lines, each of the MPC951 outputs can drive two traces giving the device an

REV 0

PLL CLOCK DRIVER

32–LEAD LQFP PACKAGE

LOW VOLTAGE

MPC951

CASE 873A–02

FA SUFFIX

Order this document

by MPC951/D

Related parts for MPC951FA

MPC951FA Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC951 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies 180MHz and output skews of 375ps the ...

Page 2

MPC951 fsela PLL_En Tclk Ref_Sel (Pull Up) PECL_CLK PECL_CLK (Pull Up) Ext_FB fselb fselc MR/OE fseld GNDO VCCO MPC951 GNDO 29 TCLK 30 PLL_En 31 Ref_Sel ...

Page 3

FUNCTION TABLE – MPC951 INPUTS fsela fselb fselc fseld ...

Page 4

MPC951 PLL INPUT REFERENCE CHARACTERISTICS ( Symbol Characteristic TCLK Input Rise/Falls f ref Reference Input Frequency f refDC Reference Input Duty Cycle 1. Maximum and minimum input reference is ...

Page 5

Using the MPC951 as a Zero Delay Buffer The external feedback of the MPC951 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay ...

Page 6

MPC951 and record peak–to–peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. If this is not the case the measurement inaccuracy will add significantly ...

Page 7

Two different configurations were chosen to look at the period displacement caused by the switching outputs. Configuration 3 is considered worst case as the “trimodal” distribution (as pictured in Figure 3) represents the largest spread between distribution peaks. Configuration 2 ...

Page 8

MPC951 When taken to its extreme the fanout of the MPC951 clock driver is effectively doubled due to its capability to drive multiple lines. MPC951 OUTPUT BUFFER MPC951 OUTPUT Z ...

Page 9

–T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM ...

Page 10

MPC951 MOTOROLA NOTES 10 TIMING SOLUTIONS ...

Page 11

TIMING SOLUTIONS BR1333 — Rev 6 NOTES 11 MPC951 MOTOROLA ...

Page 12

MPC951 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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