SI5325A-B-GM Silicon Laboratories Inc, SI5325A-B-GM Datasheet - Page 7

• Manufacturer Part Number: SI5325A-B-GM
• Description: IC UP-PROG CLK MULTIPLIER 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5325A-B-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.4GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.62 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 1.4GHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 1417 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.62 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map.
5, 10, 11,
6, 8, 31
15, 32
Pin #
12
13
16
17
21
4
Pin Name
CKIN2+
CKIN1+
CKIN2–
CKIN1–
CS_CA
GND
C2B
V
DD
Table 3. Si5325 Pin Descriptions (Continued)
GND
V
I/O
I/O
O
DD
I
I
Signal Level
LVCMOS
LVCMOS
Supply
Supply
Multi
Multi
Preliminary Rev. 0.26
CKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indi-
cator for CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present.
1 = LOS (FOS) on CKIN2.
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following Vdd pins:
5
10
32
A 1.0 µF should be placed as close to device as is practical.
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency range is 10 to 710 MHz.
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency range is 10 to 710 MHz.
Input Clock Select/Active Clock Indicator.
In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1.
1 = Select CKIN2.
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this
function and this input tristates.
In automatic clock selection mode, this pin indicates which of
the two input clocks is currently the active clock. If alarms
exist on both clocks, CA will indicate the last active clock that
was used before entering the digital hold state. The
CK_ACTV_PIN register bit must be set to 1 to reflect the
active clock status to the CA output pin.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
If CK_ACTV_PIN = 0, this pin will tristate. The CA status will
always be reflected in the CK_ACTV_REG read only register
bit.
0.1 µF
0.1 µF
0.1 µF
Description
Si5325
7