PCF8563P/F4,112 NXP Semiconductors, PCF8563P/F4,112 Datasheet - Page 20

• Manufacturer Part Number: PCF8563P/F4,112
• Description: IC REAL TIME CLK/CALENDAR 8-DIP
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendarr

Specifications of PCF8563P/F4,112

• Package / Case: 8-DIP (0.300", 7.62mm)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Function: Clock/Calendar/Alarm/Timer/Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1067-5; 935262218112; PCF8563PN

NXP Semiconductors
PCF8563
Product data sheet
Fig 13. POR override sequence
SDA
SCL
8.11.1 Power-On Reset (POR) override
power-on
8 ms
Table 27.
[1]
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I
shown in
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
Address Register name
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Registers marked x are undefined at power-up and unchanged by subsequent resets.
Figure
Control_status_1
Control_status_2
VL_seconds
Minutes
Hours
Days
Weekdays
Century_months
Years
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
CLKOUT_control
Timer_control
Timer
Register reset value
500 ns
All information provided in this document is subject to legal disclaimers.
13. All timings are required minimums.
Rev. 8 — 18 November 2010
2
2000 ns
C-bus pins, SDA and SCL, are toggled in a specific order as
Bit
7
0
0
1
x
x
x
x
x
x
1
1
1
1
1
0
x
[1]
6
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
override active
3
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Real-time clock/calendar
2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PCF8563
© NXP B.V. 2010. All rights reserved.
mgm664
1
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
2
C-bus
0
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
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