M41T11M6F STMicroelectronics, M41T11M6F Datasheet - Page 11

• Manufacturer Part Number: M41T11M6F
• Description: IC RTC SRL 512BIT 8SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/NVSRAMr

Specifications of M41T11M6F

• Memory Size: 56B
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Bus Type: Serial (2-Wire, I2C)
• User Ram: 64Byte
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOIC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4699-2

M41T11
2.2
Table 2.
1. Valid for ambient operating temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
Read mode
In this mode, the master reads the M41T11 slave after setting the slave address (see
Figure
address A
address are repeated, followed by the READ mode control bit (R/W = 1). At this point, the
master transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter
(see
The M41T11 slave transmitter will now place the data byte at address A
master receiver reads and acknowledges the new byte and the address pointer is
incremented to A
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T11
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see
t
Symbol
HD:DAT
t
t
t
t
SU:STO
HD:STA
SU:STA
SU:DAT
t
t
edge of SCL.
t
f
HIGH
LOW
SCL
BUF
t
t
R
F
Figure
8). Following the write mode control bit (R/W = 0) and the acknowledge bit, the word
(2)
n
SCL clock frequency
Clock low period
Clock high period
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(after this period the first clock pulse is generated)
START condition setup time
(only relevant for a repeated start condition)
Data setup time
Data hold time
STOP condition setup time
Time the bus must be free before a new transmission can start
is written to the on-chip address pointer. Next the START condition and slave
9). The address pointer is only incremented on reception of an acknowledge bit.
AC characteristics
n
+ 2.
Parameter
Figure 10 on page
A
= –40 to 85°C; V
(1)
CC
12).
= 2.0 to 5.5 V (except where noted).
Min
250
n
4.7
4.7
4.7
4.7
0
4
4
0
+ 1 on the bus. The
Max
100
300
1
Operation
Unit
kHz
ns
µs
11/30
µs
µs
µs
ns
µs
µs
µs
µs