ISL12026IVZ-T Intersil, ISL12026IVZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL12026IVZ-T
• Description: IC RTC/CALENDAR EEPROM 8-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12026IVZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12026IVZ-TTR

Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space, the counter “rolls over” to the start of the
address space, and the ISL12026 continues to output data
for each acknowledge received. Refer to Figure 22 for the
acknowledge and data transfer sequence.
Application Section
Crystal Oscillator and Temperature Compensation
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external
components and adjust for crystal drift over temperature and
enable very high accuracy time keeping (<5ppm drift).
SIGNALS FROM
SIGNALS FROM
SIGNALS FROM
THE MASTER
SIGNALS FROM
SDA BUS
THE SLAVE
THE MASTER
SDA BUS
THE SLAVE
19
S
T
A
R
T
1
ADDRESS
SLAVE
ADDRESS
SLAVE
1
1
FIGURE 21. RANDOM ADDRESS READ SEQUENCE
A
C
K
1
1
FIGURE 22. SEQUENTIAL READ SEQUENCE
0
A
C
K
DATA
0 0 0 0 0 0 0
(1)
ISL12026, ISL12026A
ADDRESS 1
WORD
A
C
K
A
C
K
ADDRESS 0
DATA
(2)
WORD
Frequency
Frequency
Tolerance
Turnover
Temperature
Operating Temp
Range
Parallel Load
Capacitance
Equivalent
Series
Resistance
PARAMETER
The Intersil RTC family uses an oscillator circuit with on-chip
crystal compensation network, including adjustable
load-capacitance. The only external component required is
the crystal. The compensation network is optimized for
operation with certain crystal parameters which are common
in many of the surface mount or tuning-fork crystals available
today. Table 7 summarizes these parameters.
Table 8 contains some crystal manufacturers and part numbers
that meet the requirements for the Intersil RTC products.
TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL
A
C
K
A
C
K
RTCs
A
R
(n is any integer greater than 1)
S
T
T
1
ADDRESS
MIN
SLAVE
DATA
-40
(n-1)
20
1
32.768
1
TYP
12.5
25
1
1
A
C
K
A
C
K
MAX UNITS
±100
30
85
50
DATA
DATA
(n)
ppm
kHz
kΩ
°C
°C
pF
Down to 20ppm
if desired
Typically the value
used for most
crystals
For best oscillator
performance
O
S
T
P
O
November 30, 2010
S
T
P
NOTES
FN8231.9