M48T12-200PC1 STMicroelectronics, M48T12-200PC1 Datasheet - Page 10

• Manufacturer Part Number: M48T12-200PC1
• Description: IC TIMEKPR NVRAM 16KBIT 5V 24-DI
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T12-200PC1

• Memory Size: 16K (2K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2832-5

Operation modes
2.3
Note:
10/25
Table 4.
1. Valid for ambient operating temperature: T
Data retention mode
With valid V
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
into the deselect window during the time the device is sampling V
of the power supply lines is recommended.
The power switching circuit connects external V
when V
low, an internal battery not oK (BOK) flag will be set. The BOK flag can be checked after
power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes.
on page 11
For more information on a battery storage life refer to the application note AN1012.
Symbol
t
noted).
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WLWH
WHQX
WHAX
DVWH
WHDX
WLQZ
AVWH
AVWL
EHAX
DVEH
EHDX
AVEH
AVEL
ELEH
AVAV
CC
rises above V
CC
illustrates how a BOK check routine could be structured.
WRITE mode AC characteristics
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
applied, the M48T02/12 operates as a conventional BYTEWIDE™ static
F
. The M48T02/12 may respond to transient noise spikes on V
CC
SO
Parameter
falls within the V
. As V
Doc ID 2410 Rev 8
CC
(1)
rises, the battery voltage is checked. If the voltage is too
A
= 0 to 70 °C; V
PFD
(max), V
CC
CC
to the RAM and disconnects the battery
Min Max Min Max Min Max
70
50
55
30
30
60
60
0
0
5
0
0
5
5
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
–70
PFD
25
M48T02/M48T12
(min) window. All outputs
150
120
120
90
90
10
40
40
10
10
0
0
5
5
–150
CC
. Therefore, decoupling
50
M48T02, M48T12
200
120
120
140
140
PFD
10
10
60
60
10
0
0
5
5
–200
CC
(min), the
60
CC
that reach
Figure 7
fall time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns