ISL51002CQZ-150 Intersil, ISL51002CQZ-150 Datasheet - Page 14

• Manufacturer Part Number: ISL51002CQZ-150
• Description: IC FRONT END 10BIT VID 128-MQFP
• Manufacturer: Intersil

Specifications of ISL51002CQZ-150

• Number Of Bits: 10
• Number Of Channels: 3
• Power (watts): 1.2W
• Voltage - Supply, Analog: 1.8V, 3.3V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Listing
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
ADDRESS
Red Offset LSB, (0x00)
Green Offset MSB, (0x80)
Green Offset LSB, (0x00)
Blue Offset MSB, (0x80)
Blue Offset LSB, (0x00)
PLL Htotal MSB, (0x06)
PLL Htotal LSB, (0x98)
PLL Phase, (0x00)
PLL Pre-coast, (0x04)
PLL Post-coast, (0x04)
PLL Misc, (0x00)
DC Restore and ABLC
starting pixel MSB, (0x00)
DC Restore and ABLC
starting pixel LSB, (0x02)
DC Restore Clamp Width,
(0x10)
(DEFAULT VALUE)
REGISTER
(Continued)
14
BITS
5:0
7:6
7:0
5:0
7:6
7:0
5:0
7:6
5:0
7:0
5:0
7:0
7:0
5:0
7:0
7:0
0
1
2
3
4
N/A
Red Offset LSB
Green Offset MSB
N/A
Green Offset LSB
Blue Offset MSB
N/A
Blue Offset LSB
PLL Htotal MSB
PLL Htotal LSB
PLL Sampling Phase
Pre-coast
Post-coast
PLL Lock Edge HSYNC
CLKINV ENABLE
Ext Coast SEL
Ext Coast POL
EXT CLOCK
DC Restore and ABLC
starting pixel (MSB)
DC Restore and ABLC
starting pixel (LSB)
DC Restore clamp width
FUNCTION NAME
ISL51002
2 LSBs of 10-bit offset word
ABLC off: upper 8-bits to Green offset DAC
ABLC enabled: Green digital offset
(See Red Offset)
See Red Offset
ABLC off: upper 8-bits to Blue offset DAC
ABLC enabled: Blue digital offset
(See Red Offset)
See Red Offset
14-bit HTOTAL. PLL updated on LSB write only.
PLL updated on LSB write only. SXGA default
Used to control the phase of the ADC’s sample point relative
to the period of a pixel. Adjust to obtain optimum image quality.
One step = 5.625° (1.56% of pixel period).
Number of lines the PLL will coast prior to the start of VSYNC.
Number of lines the PLL will coast after the end of VSYNC.
0: PLL locks to trailing edge of selected HSYNC (default)
1: PLL locks to leading edge of selected HSYNC
0: CLKINV input ignored
1: CLKINV input enabled
0: Internal COAST generation
1: External COAST source
0: Active high external COAST
1: Active low external COAST
0: Internal pixel clock from DPLL
1: External pixel clock from EXTCLKin pin
Pixel after Raw HSYNC trailing edge to begin DC restore and
ABLC. 14-bits.
Only applies to DC restore clamp used for AC-coupled
configurations. A value of 0x00 means the clamp DAC is
never connected to the input.
DESCRIPTION
September 19, 2007
FN6164.2