CS5521-ASZ Cirrus Logic Inc, CS5521-ASZ Datasheet
CS5521-ASZ
Specifications of CS5521-ASZ
Available stocks
Related parts for CS5521-ASZ
CS5521-ASZ Summary of contents
Page 1
... AIN4+ AIN4- NBV CPD http://www.cirrus.com General Description The CS5521/22/23/24/28 are highly integrated ∆Σ ana- log-to-digital converters (ADCs) which use charge- balance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) performance. The ADCs come as either (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instru- mentation amplifier ...
Page 2
... TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7 TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... DIGITAL CHARACTERISTICS........................................................................................... DIGITAL CHARACTERISTICS........................................................................................... 9 DYNAMIC CHARACTERISTICS ............................................................................................ 10 RECOMMENDED OPERATING CONDITIONS ..................................................................... 10 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10 SWITCHING CHARACTERISTICS ........................................................................................ 11 2 ...
Page 3
... PCB Layout ................................................................................................................... 47 3. PIN DESCRIPTIONS .............................................................................................................. 48 3.1 Clock Generator .............................................................................................................. 49 3.2 Control Pins and Serial Data I/O ..................................................................................... 49 3.3 Measurement and Reference Inputs ............................................................................... 49 3.4 Power Supply Connections ............................................................................................. 50 4. SPECIFICATION DEFINITIONS ............................................................................................. 51 5. ORDERING INFORMATION .................................................................................................. 52 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 52 7. PACKAGE DIMENSION DRAWINGS ................................................................................... 53 DS317F4 CS5521/22/23/24/28 3 ...
Page 4
... Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations ............................................................................................................. 15 Table 2. Command Register Quick Reference.............................................................................. 19 Table 3. Channel-Setup Registers ................................................................................................ 27 Table 4. Configuration Register..................................................................................................... 30 Table 5. Offset and Gain Registers ............................................................................................... 31 Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28 ...................................... 40 REVISION HISTORY Revision Date F3 May 2003 ...
Page 5
... N 4. Drift over specified temperature range after calibration at power-up at 25° Measured with Charge Pump Drive off. 6. All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode. DS317F4 (T = 25° C; VA+, VD ±5%; VREF+ = 2.5 V, VREF- = AGND, ...
Page 6
... The maximum full scale signal can be limited by saturation of circuitry within the internal signal path. 6 (Continued) Min Bipolar/Unipolar Mode -0.150 NBV 1.85 0.0 (Note (Note (VREF-)+1 NBV (Note Bipolar/Unipolar Mode 0.40 1.0 2.0 Bipolar/Unipolar Mode - - (Note CS5521/22/23/24/28 Typ Max Unit - 0.950 VA+ V 100 300 pA/° 120 - dB 120 - 2.5 VA ...
Page 7
... Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5521/23’s output conversions are 16 bits. Noise free Resolution numbers are based upon VREF = 2.5 V and XIN = 32.768 kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor ...
Page 8
... Input Range, (Bipolar Mode 100 CS5521/22/23/24/ 2 1.5 µV 3 µV 6 µV 2 µV 4 µV 8 µV 2.5 µV 6 µV 11.5 µV 4.5 µV 10 µV 20 µV 16 µV 45 µV 85 µV 72 µV 195 µV 350 µV 340 µV 900 µ 1 5.3 mV (Note 17 2.5 V ...
Page 9
... C; VA ±5%; VD+ = 3.0 V ±10%; GND = 0; A Symbol V IH XIN SCLK V IL XIN SCLK -400 µA out CPD -4.0 mA out SDO -5.0 mA out 400 µA out CPD out SDO 5.0 mA out out CS5521/22/23/24/28 Min Typ Max Unit 0.6 VD (VD+)-0 (VD 0.6 (VA (VD (VD ...
Page 10
... Positive Digital VD+ Positive Analog VA+ Negative Potential NBV (Note 22 and 23 OUT (Note 24) PDN VREF pins V INR AIN Pins V INA V IND stg CS5521/22/23/24/28 Ratio Unit XIN/4 Hz 1/f out Min Typ Max Unit 2.7 5.0 5.25 V 4.75 5.0 5.25 V 1.0 2.5 VA+ V -1.8 -2.1 -2 ...
Page 11
... CS Rising to SDO Hi-Z Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz (CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput. 26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source ...
Page 12
... Figure 1. Continuous Running SCLK Timing (Not to Scale Figure 2. SDI Write Timing (Not to Scale Figure 3. SDO Read Timing (Not to Scale) CS5521/22/23/24/ DS317F4 ...
Page 13
... Sps, and 101.1 Sps (XIN = 32.768 kHz). The devices are capable of producing output update rates up to 617 Sps when a 200 kHz clock is used (CS5522/24/28 401 Sps using a 130 kHz clock (CS5521/23). Further note that the digital fil- CS5522 AIN2+ AIN2- ...
Page 14
... VA+ and from the NBV (Negative Bias Voltage) pin CS5521/22/23/24/ operated in either of two analog input configurations. The NBV pin can be bi- ased to a negative voltage between -1.8 V and -2 tied to AGND (for the CS5528, NBV has to be between -1.8 V and -2.5 V for the ranges below 100 mV when the amplifier is engaged) ...
Page 15
... VREF voltage divided by the Gain Factor. See Table 1 to determine if the CS5521/22/23/24/28 is being used properly. For example, in the 55 mV range, to determine the nominal input voltage to the modulator, divide VREF (2 the Gain Fac- tor (2 ...
Page 16
... Application Note 158 for more details on high-voltage (>5 V) measurement. 2.1.5 Voltage Reference The CS5521/22/23/24/28 devices are specified for operation with a 2.5 V reference voltage between the VREF+ and VREF- pins of the device. For a single-ended reference voltage, such as the LT1019-2.5, the reference voltage is input into the VREF+ pin of the converter and the VREF- pin is grounded ...
Page 17
... Table 2 can be used to decode all valid commands (the first 8 bits into the serial port). 4 (24 Gain 1 Setup 1 Setup 2 Gain 2 Setup 3 Setup 4 Gain 3 Setup 5 Setup 6 Gain 4 Setup 7 Setup Configuration Latch Outputs Channel Select Output Word Rate PGA Selection Unipolar/Bipolar Figure 9. CS5523/24 Register Diagram CS5521/22/23/24/ DATA FIFO SDO 17 ...
Page 18
... System Initialization When power to the CS5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 kHz oscillator has started and a counter- timer elapses. Due to the high Q of the 32.768 kHz crystal, the oscillator takes 400-600 ms to start. The counter-timer counts 2006 oscillator clock cycles to make sure the oscillator is fully stable ...
Page 19
... Write to selected register. 1 Read from selected register. 000 Reserved 001 Offset Register 010 Gain Register 011 Configuration Register 101 Channel Set-up Registers - register is 48-bits long for CS5521/22 - register is 96-bits long for CS5523/24 - register is 192-bits long for CS5528 110 Reserved 111 Reserved CSRP0 CC2 ...
Page 20
... Gain Register 2 (All devices) 010 Gain Register 3 (CS5523/24/28 only) 011 Gain Register 4 (CS5523/24/28 only) 100 Gain Register 5 (CS5528 only) 101 Gain Register 6 (CS5528 only) 110 Gain Register 7 (CS5528 only) 111 Gain Register 8 (CS5528 only CS1 CS0 R CS1 CS0 R/W CS5521/22/23/24/ DS317F4 ...
Page 21
... CSRs accessed is determined by the device being used and the number of CSRs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels ac- cessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for the CS5523/24, and 192-bits (16 Setups) long for the CS5528. ...
Page 22
... Setup 7 (CS5523/24/28) 0111 Setup 8 (CS5523/24/28) 1000 Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) 1101 Setup 14 (CS5528 only) 1110 Setup 15 (CS5528 only) 1111 Setup 16 (CS5528 only CSRP1 CSRP0 CS5521/22/23/24/ DS317F4 ...
Page 23
... Setup 14 (CS5528 only) 1110 Setup 15 (CS5528 only) 1111 Setup 16 (CS5528 only) CC [2:0] (Calibration Control Bits) 000 Reserved 001 Self-Offset Calibration 010 Self-Gain Calibration 011 Reserved 100 Reserved 101 System-Offset Calibration 110 System-Gain Calibration 111 Reserved DS317F4 CSRP1 CSRP0 CS5521/22/23/24/ CC2 CC1 CC0 23 ...
Page 24
... SYNC1 D7(MSB Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode CS5521/22/23/24/ DS317F4 ...
Page 25
... Serial Port Interface The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, SDI, SDO. Figure 10 illustrates the serial sequence necessary to write to, or read from the serial port’s registers. CS (Chip Select) is the control line which enables access to the serial port. If the CS pin is tied low, the port can function as a three-wire interface ...
Page 26
... Reading/Writing the Channel-Setup Reg- isters The CS5521/22 have two 24-bit channel-setup reg- isters (CSRs). The CS5523/24 have four CSRs, and the CS5528 has eight CSRs (refer to Table 3 for more detail on the CSRs). These registers are ac- cessed in conjunction with the depth pointer bits in the configuration register ...
Page 27
... V 100 5.0 V 101 2.5 V 110 Not used. 111 Not used Bipolar measurement mode. 1 Unipolar measurement mode. Table 3. Channel-Setup Registers CS5521/22/23/24/28 CSR #1 Setup 1 Setup 2 Bits <191:180> Bits <179:168> #8 Setup 15 Setup 16 Bits <23:12> Bits <11:0> CS5528 D16 D15 D14 D13 ...
Page 28
... Power Consumption Control Bits The CS5522/24/28 devices accommodate four power consumption modes: normal, low power, standby, and sleep. The CS5521/23 accommodate three power consumption modes: normal, standby, and sleep. The normal (default) mode is entered af- ter a power-on reset. In normal mode, the ...
Page 29
... CS5522/24/28 typically consume 9.0 mW. The CS5521/23 typically consume 6.0 mW. The low- power mode is an alternate mode in the CS5522/24/28 that reduces the consumed power to 5.5 mW entered by setting bit D8 (the low- power mode bit) in the configuration register to logic 1. Slightly degraded noise or linearity perfor- mance should be expected in the low-power mode ...
Page 30
... Bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode), or when the input is more neg- ative than the negative full scale (bipolar mode). 0000 R Must always be logic 0. Table 4. Configuration Register CS5521/22/23/24/28 D16 D15 D14 D13 RC ...
Page 31
... Calibration The CS5521/22/23/24/28 offer four different cali- bration functions including self calibration and sys- tem calibration. However, after the devices are reset, the converter is functional and can perform measurements without being calibrated. In this case, the converter will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words for the ± ...
Page 32
... As shown in Figures 16 and 17, the user must input a signal representing the positive full-scale point to AIN+ + AIN- - VREF- Figure 12. Self Calibration of Offset (High Ranges) OPEN + External Connections AIN OPEN CLOSED AIN CLOSED Figure 14. System Calibration of Offset (Low Ranges) CS5521/22/23/24/28 applied to the converters. S1 OPEN + + X20 - - S2 OPEN S4 CLOSED + + X20 - - ...
Page 33
... Full-scale input must not saturate the 20X in- strumentation amplifier, if the calibration input range where the instrumentation am- plifier is involved. DS317F4 CS5521/22/23/24/28 2) The 1’s density of the modulator must not be greater than 80 percent (the input to the ∆Σ modulator must not exceed the maximum input which Table 1 specifies). ...
Page 34
... While reading, note that the CS5521/22 have a FIFO which is four words deep. The CS5523/24 have a FIFO which is eight words deep and the CS5528 has a FIFO which is sixteen ...
Page 35
... The ADC will then perform a single conversion on the referenced Setup, and SDO will fall to indi- cate that the conversion is complete. Thirty-two DS317F4 CS5521/22/23/24/28 SCLKs are then needed to read the conversion word from the data register. The first 8 SCLKs are used to clear the SDO flag. During the last 24 SCLKs, the data word will be output from the con- verter on the SDO line ...
Page 36
... To exit this conversion mode, "1111 1111" must be provided on SDI during the first 8 SCLKs. If the user decides to exit, 24 more SCLKs are re- 36 CS5521/22/23/24/28 quired to read the final conversion word from the data register and return to command mode. 2.4.1.4 Single, Multiple-Setup Conversions ...
Page 37
... SCLKs are used to clear the SDO flag. Ev- ery 24 bits thereafter consist of the data words of each Setup that was referenced, until all of the data DS317F4 CS5521/22/23/24/28 has been read from the part. If, during the first 8 SCLKs, "00000000" is provided on SDI, the con- verter will remain in this conversion mode, and continue to perform conversions on the desired number of Setups ...
Page 38
... One final note is that only one calibration is performed with each command byte. To calibrate all the channels additional calibration commands are necessary. 38 CS5521/22/23/24/28 2.4.3 Example of Using the CSRs to Perform Conversions and Calibrations Any time a calibration command is issued (CB=1 and proper CC2-CC0 bits set) or any time a normal ...
Page 39
... Once the calibration is completed, SDO falls. To perform additional calibrations, more commands have to be issued. Notes: 1)The configuration register must be written before 2) The CSRs need to be written regardless of single 3) When single-Setup conversions ( are de- CS5521/22/23/24/28 mode the user must channel-setup registers (CSRs) because the depth information contained in the configuration regis- ter defines how many of the CSRs to use ...
Page 40
... Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between ± full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28 40 the conversions MSB first. The last byte of the con- version data word (CS5521/23 only) contains data monitoring flags ...
Page 41
... Conversion Data Bits [23:8 for CS5521/23; 23:0 for CS5522/24/28] These bits depict the latest output conversion. OD (Oscillation detect Flag Bit) 0 Bit is clear when oscillatory condition in modulator does not exist (bit is read only). 1 Bit is set any time an oscillatory condition is detected in the modulator. This does not occur under normal operation conditions, but may occur when the input is extremely overranged ...
Page 42
... The converters will operate with an external (CMOS compatible) clock with frequencies up to 130 kHz (CS5521/23) or 200 kHz (CS5522/24/28). Figures 19 and 20 detail the CS5521/23 and CS5522/24/28’s performance (respectively) at in- creased clock rates. The 32.768 kHz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over tempera- ture ...
Page 43
... Power Supply Arrangements The CS5521/22/23/24/28 A/D converters are de- signed to operate from a single +5 V analog supply and a single + digital supply. A -2.1 V supply is usually generated from the charge pump drive to provide power to the instrumentation am- plifier’s NBV (negative bias voltage) pin. Figure 21 illustrates the CS5522 connected with analog supply and with the external compo- nents required for the charge pump drive ...
Page 44
... Figure 22. CS5522 Configured for ground-referenced Unipolar Signals + alo Figure 23. CS5522 Configured for Single Supply Bridge Measurement Ω µ S5522 Ω 0.1 µ S5522 CS5521/22/23/24/ µ ptio rce ria ata In te rfa 0.1 µ 32. 0kH tio urce ria l D ata 8 Inte rfa DS317F4 ...
Page 45
... CS5525/26 Charge Pump Drive for External Loads” for more details on using the charge pump with exter- nal loads. 2.9 Digital Gain Scaling The CS5521/22/23/24 and CS5528 all feature a gain register capable of being scaled from 0 - decimal. The specified ranges of the con- verter are defined with a voltage reference of 2 ...
Page 46
... The converters include an on-chip, power-on reset circuit to automatically reset the ADCs shortly af- ter power CS5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 kHz oscillator has started and a counter-timer elapses. The counter-timer counts 2006 oscillator clock cycles to make sure the oscillator is fully stable. During ...
Page 47
... Monitor the SDO pin for a flag that the data is ready and read conversion data. 2.11 PCB Layout The CS5521/22/23/24/28 should be placed entirely over an analog ground plane with both the AGND and DGND pins of the device connected to the an- alog plane. Place the analog-digital plane split im- mediately adjacent to the digital portion of the chip ...
Page 48
... AIN5+ AIN7+ SINGLE-ENDED ANALOG INPUT 5 20 AIN6+ AIN8+ SINGLE-ENDED ANALOG INPUT 6 19 NBV A1 LOGIC OUTPUT SCLK SERIAL CLOCK INPUT 8 17 CPD VD+ POSITIVE DIGITAL POWER 9 16 SDI DGND DIGITAL GROUND SDO SERIAL DATA OUT 11 14 CRYSTAL OUT XIN XOUT 12 13 CS5521/22/23/24/28 DS317F4 ...
Page 49
... Differential input pins into the CS5522 and CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input. Single-ended input pins into the CS5528. VREF+, VREF- - Voltage Reference Input. Fully differential inputs which establish the voltage reference for the on-chip modulator. DS317F4 CS5521/22/23/24/28 49 ...
Page 50
... Square wave output used to provide energy for the charge pump. 3.4 Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. Nominally +5 V. VD+ - Positive Digital Power. Positive digital supply voltage. Nominally +3 AGND - Analog Ground. Analog Ground. DGND - Digital Ground. Digital Ground. 50 CS5521/22/23/24/28 DS317F4 ...
Page 51
... AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. DS317F4 CS5521/22/23/24/28 51 ...
Page 52
... CS5528-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Package CS5521-AS 20-pin 0.2" Plastic SSOP CS5521-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) CS5522-AP 20-pin 0.3" Plastic DIP CS5522-AS 20-pin 0.2" Plastic SSOP CS5522-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) CS5523-AS 24-pin 0.2" ...
Page 53
... JEDEC # : MS-001 Controling Dimension is Inches CS5521/22/23/24/ ∝ SIDE VIEW MILLIMETERS MIN NOM MAX 0.00 -- 0.38 0.508 2.92 3.302 0.36 0.4572 1.14 1.46 ...
Page 54
... JEDEC # : MS-001 Controling Dimension is Inches CS5521/22/23/24/ ∝ SIDE VIEW MILLIMETERS MIN NOM MAX 0.00 -- 0.38 0.51 2.92 3.30 0.36 0.46 1.14 1.46 ...
Page 55
... JEDEC #: MO-150 Controling Dimension is Millimeters. CS5521/22/23/24/ ∝ END VIEW L MILLIMETERS NOM MAX -- -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 7.20 7.50 7.80 8.20 5 ...
Page 56
... JEDEC #: MO-150 Controling Dimension is Millimeters. CS5521/22/23/24/ ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...