ADC083000CIYB/NOPB National Semiconductor, ADC083000CIYB/NOPB Datasheet - Page 29

• Manufacturer Part Number: ADC083000CIYB/NOPB
• Description: IC ADC 8BIT 3GSPS LP 128-LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC083000CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 2.3W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC083000CIYB; *ADC083000CIYB/NOPB; ADC083000CIYB

Bit 15:7
Bits 6:0
Bit 15:7
Bit 6:0
(MSB)
Addr: 3h (0011b)
Addr: Dh (1101b)
(MSB)
(LSB)
(LSB)
D15
D15
D7
D7
D14
D14
D6
D6
Extended Clock Phase Adjust Fine
1
1
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the ADC is adjusted
linearly and monotonically with a 9 bit data
value. The adjustment range is ±20% of the
nominal 700 mV
0000 0000 0
1000 0000 0
Default Value
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b
Must be set to 1b
Fine Adjust Magnitude. With all bits set, total
adjust = 110ps of non-linear clock adjust.
Refer to Section 2.3.1.
POR State: 000 0000 0b
Must be set to 1b
Full-Scale Voltage Adjust
D13
D13
D5
D5
1
1
D12
D12
D4
D4
1
1
Adjust Value
P-P
FAM
D11
D11
560mV
700mV
840mV
D3
D3
1
differential value.
1
D10
D10
P-P
P-P
P-P
D2
D2
1
1
W only (0x807F)
W only (0x007F)
D9
D1
D9
D1
1
1
D8
D0
D8
D0
1
1
29
Bit 15
Bit 14:11
Bit 10
Bits 9:0
Bits 15:12 Must be set to 1b
Bit 11
Bit 10:0
Addr: Eh (1110b)
Addr: Fh (1111b)
ENA
D15
D15
D7
D7
1
1
1
Extended Clock Phase Adjust Coarse
D14
D14
D6
D6
1
1
1
ENAble Clock Phase Adjust, default is 0b.
RTD bit MUST also be set to ensure proper On
Command Calibration with Clock Phase
Adjust enabled.
Coarse Adjust Magnitude. Each LSB results in
approximately 70ps of clock adjust. Refer to
Section 2.3.1.
POR State: 0000b
Low Frequency Sample clock. When this bit is
set 1b, the dynamic performance of the device
is improved when the sample clock is less than
900MHz.
POR State: 0b
Must be set to 1b
TPO: Test Pattern Output enable. When this
bit is set 1b, the ADC is disengaged and a test
pattern generator is connected to the outputs
including OR. This test pattern will work with
the device in the SDR and DDR modes.
POR State: 0b
Must be set to 1b
D13
D13
D5
D5
Test Pattern Register
1
1
1
CAM
D12
D12
D4
D4
1
1
1
TPO
D11
D11
D3
D3
1
1
D10
LFS
D10
D2
D2
1
W only (0xF7FF)
1
1
W only (0x03FF)
D9
D1
D9
D1
1
1
1
1
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D8
D0
D8
D0
1
1
1
1