MAX1403EAI+ Maxim Integrated Products, MAX1403EAI+ Datasheet - Page 8

• Manufacturer Part Number: MAX1403EAI+
• Description: IC ADC 18BIT LP 28-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1403EAI+

• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 21.45mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Number Of Adc Inputs: 5
• Architecture: Delta-Sigma
• Conversion Rate: 4.8 KSPs
• Resolution: 18 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: External
• Supply Voltage (max): 3 V
• Maximum Power Dissipation: 21.45 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Signal Type: Pseudo-Differential, Differential
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
TIMING CHARACTERISTICS (continued)
(V+ = +2.7V to +3.6V, V
T
Figure 1. Load Circuit for Bus-Relinquish Time and V
V
8
Note 20: All input signals are specified with t
Note 21: See Figure 4.
Note 22: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with SCLK
Note 23: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1403 is not in standby mode. If no
Note 24: The MAX1403 is production tested with f
Note 25: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
Note 26: For read operations, SCLK active edge is falling edge of SCLK.
Note 27: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is
Note 28: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
Note 29: Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
MAX
CS Falling Edge to SCLK Falling
Edge Setup Time
Data Valid to SCLK Rising Edge
Setup Time
Data Valid to SCLK Rising Edge
Hold Time
SCLK High Pulse Width
SCLK Low Pulse Width
CS Rising Edge to SCLK Rising
Edge Hold Time
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21, 29)
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21, 29)
OH
_______________________________________________________________________________________
Levels
, unless otherwise noted.) (Notes 20, 21, 22)
OUTPUT
PIN
TO
PARAMETER
idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted and
the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently tied
low, the part should only be operated with SCLK idling high between accesses.
clock is present, the device can draw higher current than specified.
then extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quot-
ed in the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
careful not to allow subsequent reads to occur close to the next output update.
50pF
DD
= +2.7V to +3.6V, AGND = DGND, f
SYMBOL
t
t
t
t
t
t
t
t
13
14
15
16
17
18
19
20
100µA
at V
100µA
at V
DD
DD
r
= +3.3V
= +3.3V
= t
f
= 5ns (10% to 90% of V
CLKIN
OL
and
at 2.5MHz (1MHz for some I
CONDITIONS
CLKIN
= 2.4576MHz, input logic 0 = 0V, logic 1 = V
DD
) and timed from a voltage level of 1.6V.
DD
tests).
MIN
100
100
30
30
40
0
0
0
TYP
OL
MAX
DD
or V
, T
OH
A
= T
limits.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
MIN
to