LTC1298IS8 Linear Technology, LTC1298IS8 Datasheet - Page 10

• Manufacturer Part Number: LTC1298IS8
• Description: IC A/D CONV SAMPLING 12BIT 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1298IS8

• Number Of Bits: 12
• Sampling Rate (per Second): 11.1k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1286/LTC1298
APPLICATION INFORMATION
10
SERIAL INTERFACE
The 2-channel LTC1298 communicates with micropro-
cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1286 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving systems.
The LTC1286 does not require a configuration input word
and has no D
shown in the LTC1286 operating sequence. After CS falls
the second CLK pulse enables D
D
D
CLK
OUT
CLK
OUT
CS
CS
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t
DATA
t
SMPL
t
HI-Z
SMPL
HI-Z
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
t
suCS
t
suCS
IN
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
NULL
NULL
pin. A falling CS initiates data transfer as
BIT
BIT
(MSB)
(MSB)
B11
B11
U
B10
B10
U
B9
B9
B8
B8
OUT
B7
B7
t
t
W
CONV
CONV
. After one null bit the
t
CYC
B6
B6
Figure 1. LTC1286 Operating Sequence
B5
B5
B4
B4
U
B3
B3
t
CYC
B2
B2
B1
B1
B0*
B0
A/D conversion result is output on the D
CS high resets the LTC1286 for the next data exchange.
The LTC1298 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, D
together allowing transmission over just 3 wires: CS, CLK
and DATA (D
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1298 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
D
conversion. After one null bit, the result of the conversion
is output on the D
CS should be brought high. This resets the LTC1298 in
preparation for the next data exchange.
IN
B1
t
DATA
input which configures the LTC1298 and starts the
HI-Z
POWER
DOWN
B2
B3
NULL
IN
BIT
B4
/D
OUT
B11
OUT
B5
POWER DOWN
).
B10 B9
line. At the end of the data exchange
B6
t
DATA
B7
B8
B8
IN
B9
and D
B10
B11*
OUT
OUT
line. Bringing
may be tied
LTC1286/98 • F01
HI-Z