MAX1186ECM+TD Maxim Integrated Products, MAX1186ECM+TD Datasheet - Page 11

• Manufacturer Part Number: MAX1186ECM+TD
• Description: IC ADC 10BIT 40MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1186ECM+TD

• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1186 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every one-half clock cycle. Including
the delay through the output latch, the total clock-cycle
latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con-
verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5 clock
cycles later) and CHB data is updated on the falling
edge (5.5 clock cycles later) of the clock signal. The A/B
indicator follows the clock signal with a typical delay
Figure 1. Pipelined Architecture—Stage Blocks
Internal Reference and Multiplexed Parallel Outputs
V
IN
V
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
INA
T/H
FLASH
ADC
______________________________________________________________________________________
1.5 BITS
STAGE 1
Detailed Description
T/H
DAC
DIGITAL CORRECTION LOGIC
Σ
STAGE 2
10
x2
V
OUT
STAGE 8
2-BIT FLASH
STAGE 9
ADC
MULTIPLEXER
D0A/B–D9A/B
OUTPUT
V
time of 6ns and remains high when CHA data is updat-
ed and low when CHB data is updated.
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track- and hold-
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully-differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out-
put of the amplifier and switch S4c is closed. The result-
ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang-
ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1186 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA-,
as well as INB+ and INB-, and set the common-mode
voltage to midsupply (V
IN
10
V
INB
T/H
FLASH
ADC
1.5 BITS
Input Track-and-Hold (T/H) Circuits
STAGE 1
T/H
DAC
DIGITAL CORRECTION LOGIC
Σ
STAGE 2
DD
10
/ 2) for optimum performance.
x2
V
OUT
STAGE 8
2-BIT FLASH
STAGE 9
ADC
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