AD7683BRM Analog Devices Inc, AD7683BRM Datasheet - Page 12

• Manufacturer Part Number: AD7683BRM
• Description: IC ADC 16BIT 100KSPS 8-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7683BRM

• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 6mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7683CBZ - BOARD EVALUATION FOR AD7683
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7683
APPLICATIONS INFORMATION
CIRCUIT INFORMATION
The AD7683 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture.
The AD7683 is capable of converting 100,000 samples per
second (100 kSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it consumes typi-
cally 150 μW with a 2.7 V supply, ideal for battery-powered
applications.
The AD7683 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an
8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package.
The AD7683 is an improved second source to the ADS8320 and
ADS8325. For even better performance, consider the AD7685.
CONVERTER OPERATION
The AD7683 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors that connect
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and −IN inputs. When the
acquisition phase is complete and the CS input goes low, a con-
version phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Therefore, the differential voltage between the inputs,
+IN and −IN, captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
GND
REF
+IN
–IN
32,768C
32,768C
16,384C
16,384C
MSB
MSB
Figure 20. ADC Simplified Schematic
4C
4C
Rev. A | Page 12 of 16
2C
2C
C
C
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (V
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7683 is shown in Figure 21
and Table 9.
Table 9. Output Codes and Ideal Input Voltages
Description
FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
1
2
This is also the code for an overranged analog input (V
V
This is also the code for an underranged analog input (V
REF
– V
C
C
GND
000...010
000...001
000...000
111...101
111...111
111...110
).
LSB
LSB
–FS + 0.5 LSB
–FS
SW+
SW–
Figure 21. ADC Ideal Transfer Function
COMP
Analog Input
V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 μV
0 V
–FS + 1 LSB
SWITCHES CONTROL
REF
= 5 V
CONTROL
LOGIC
ANALOG INPUT
CNV
REF
/2, V
Digital Output Code
Hexadecimal
FFFF
8001
8000
7FFF
0001
0000
BUSY
OUTPUT CODE
+FS – 1.5 LSB
REF
1
2
/4...V
+IN
+FS – 1 LSB
+IN
– V
REF
– V
–IN
/65,536).
–IN
above
below V
GND
).