LTC1294CCSW#TR Linear Technology, LTC1294CCSW#TR Datasheet - Page 21

• Manufacturer Part Number: LTC1294CCSW#TR
• Description: IC DATA ACQ SYS 12BIT 5V 20SOIC
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1294CCSW#TR

• Resolution (bits): 12 b
• Sampling Rate (per Second): 46.5k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Dual ±
• Voltage - Supply: ±5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Usually V
on the “–” input to generate a 0.25LSB error (300µV) with
the converter running at CLK = 1MHz, its peak value would
have to be 66mV. Rearranging the above equation the
maximum sinusoidal signal that can be digitized to a given
accuracy is given as:
For 0.25LSB error (300µV) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Unused inputs should be tied to the ground plane.
Reference Input
The voltage on the reference input of the LTC1293/4/6
determines the voltage span of the A/D converter. The
reference input has transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 12). During each bit test of the conversion
(every CLK cycle) a capacitive current spike will be gener-
ated on the reference pin by the A/D. These current spikes
settle quickly and do not cause a problem. If slow settling
circuitry is used to drive the reference input, take care to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
A
Figure 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time for
the reference to settle. Even at the maximum CLK rate of
1MHz most references and op amps can be made to settle
within the 1µs bit time. For example the LT1027 will settle
adequately or with a 10µF bypass capacitor at V
LT1021 also can be used.
PPLICATI
f
(–)
MAX
Figure 12. Reference Input Equivalent Circuit
ERROR
R
V
OUT
REF
=
⎛
⎜
⎝
V
will not be significant. For a 60Hz signal
ERROR MAX
O
2
REF+
REF–
13
14
π
U
V
PEAK
S
(
I FOR ATIO
U
)
⎞
⎟
⎠
⎛
⎜
⎝
EVERY CLK CYCLE
f
R
12
CLK
ON
W
⎞
⎟
⎠
LTC1293/4/6
8pF – 40pF
LTC 1293 F12
U
REF
the
Reduced Reference Operation
The effective resolution of the LTC1293/4/6 can be in-
creased by reducing the input span of the converter. The
LTC1293/4/6 exhibits good linearity over a range of refer-
ence voltages (see typical performance characteristics
curves of Change in Linearity vs Reference Voltage and
Change in Gain Error vs Reference Voltage). Care must be
taken when operating at low values of V
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. Offset and Noise are
factors that must be considered when operating at low
V
AGND pin. Any voltage drop from the AGND pin to the
ground plane will cause a gain error.
Offset with Reduced V
The offset of the LTC1293/4/6 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical performance characteris-
tic curve of Unadjusted Offset Error vs Reference Voltage
shows how offset in LSB’s is related to reference voltage
for a typical value of V
which is 0.1LSB with a 5V reference becomes 0.4LSB with
REF
Figure 14. Poor Reference Settling Can Cause A/D Errors
values. For the LTC1293 REF
Figure 13. Adequate Reference Settling (LT1027)
LTC1293/LTC1294/LTC1296
HORIZONTAL: 1µs/DIV
HORIZONTAL: 1µs/DIV
OS
REF
. For example a V
–
has been tied to the
REF
because of the
OS
of 0.1mV,
21
129346fs