AS8500-ASOU austriamicrosystems, AS8500-ASOU Datasheet
AS8500-ASOU
Specifications of AS8500-ASOU
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AS8500-ASOU Summary of contents
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... Reprogramming is at any time possible by just writing into two internal registers via the serial interface. The AS8500 has four ground refering inputs which can be switched separately to the internal PGA. Two input channels can also be operated as a fully differential ground free input. The system can measure both positive and negative input signals ...
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... ROUND CONNECTION 9.2 T EMF.............................................................................................................................................................................. 35 HERMAL 9.3 N OISE CONSIDERATIONS 9 ................................................................................................................................................................... 36 HIELDING GUARDING 10 TYPICAL PERFORMANCE CHARACTERISTICS.......................................................................................................................... 37 11 PACKAGE DIMENSIONS................................................................................................................................................................ 39 12 REVISION HISTORY ....................................................................................................................................................................... 39 13 ORDERING INFORMATION............................................................................................................................................................ 39 14 CONTACT........................................................................................................................................................................................ 40 14.1 H ...................................................................................................................................................................... 40 EADQUARTERS 14 ....................................................................................................................................................................... 40 ALES FFICES Revision 1.2, 08-Junel-06 CONTENTS ............................................................................................................................................ 9 ................................................................................................................................................................ 16 ....................................................................................................................................................... 30 ....................................................................................................................................... 35 ANALOG COMMON ................................................................................................................................................................ 35 www.austriamicrosystems.com Page ...
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... VDDD to reduce current consumption the user must provide a serial clock on this input signal wake-up to external µ C must be connected to VSS with capacitor this PIN must be connected with a 50-100nF-capacitor to VSS; no direct connection to VSSD/VSS allowed www.austriamicrosystems.com Comment Page ...
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... Jedec Std – 020C, lead free Revision 1.2, 08-Junel-06 SYMBOL MIN TYP VDD -0 -0.3 VDD +0.3 I -100 SCR ESD - -55 STRG T LEAD 5 R thJA P TOT www.austriamicrosystems.com MAX UNIT NOTE 7.0 V Polarity inversion externally protected V 100 mA JEDEC 125 O C (Tj = 150°C) 150 C O 260 ° ...
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... TC value at elevated temperature G50 and G100 are recommended for applications in the temperature range 0 to 85°C 7 Revision 1.2, 08-Junel-06 conditions min typ 6, 24, 50, 100 °C -40 to 125° °C -40 to 125° ° °C G1 -300 to + 800 G6 G24 G50 G100 www.austriamicrosystems.com max units 0.4 % @-120mV 1.0 % @-120mV 0.2 % @+-20mV 0.6 % @+-20mV 1 % @+-10mV 1 % @+-5mV mV +/- 120 mV +/- 30 ...
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... 100 1000 Hz room temperature room temperature 4.9 to 5.1 V www.austriamicrosystems.com max units % 0 digits 2) 0. digits 2) 0. digits 2) 0. digits ppm/K 0.2 0.5 µ ...
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... Rload > 50 kOhm 64 7.8 1 0.05 180 RSHH, VBAT, ETS, ETS Ue < 150 typical -20 to 100°C output to RSHH, RSHL www.austriamicrosystems.com typ max units 16 bits 1. ppm/K 200 Ohm 4.096 MHz 128 4 8 1000 16000 ...
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... VDDD=5V, Vih=5V -1 VDDD=5V, Vil=0 30 output PINs SDAT and INTN VDDD=5V, -633uA 4.5 VDDD=5V, 564uA VDDD=5V, -633uA 4.5 VDDD=5V, 564uA VDDD=5V -1 VDDD=5V 3.5 VDDD=5V VDDD=VDDA=5V VDDD=VDDA=5V 4.7 4.5 www.austriamicrosystems.com max units 248 µ µ A 900 ppm/K 0.001 µ MOhm V 1 µ A 120 µ ...
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... SDI interface. For more details of the input multiplexer see the following schematic. The position of all switches is defined by writing into the registers CRA, CRB and CRG via the SDI bus, which is explained in 7.5.2 through 7.5.4. Revision 1.2, 08-Junel- www.austriamicrosystems.com Page ...
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... The absolute value and its temperature coefficient (TC) is given by the content of the TRR register. This opens the possibility to calibrate the reference voltage to the optimum absolute value (i.e. 1.28 V) and the TC value to zero thus eliminating fully the production spread. Revision 1.2, 08-Junel-06 41 INTERNAL CURRENT TEMPERA SOURCE TURE AD- CON- PGA VERTER measurement open loop value resistance load in kOhm www.austriamicrosystems.com 90 100 110 Page 10 of ...
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... The same is repeated at any temperature above RT. From these data the TRIMBTC setting for a minimum drift can be easily calculated. Revision 1.2, 08-Junel- function of temperature 75 °C 24 ° content of TRIMBV in bits change 12.7 ppm setting of subregister TRIMBTC of TRR www.austriamicrosystems.com 25 30 per step Page 11 of ...
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... Current sources The AS8500 contains several current sources which can be used for checking all input lines for wire brake, to control external circuitry or to activate external sensors. Main current source The main current source can be digitally controlled via the content of the CRG register in 31 steps of 8 µ the range 248 µ A. Its absolute value can be calibrated by writing in the subregister TRIMC of TRR ...
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... TC calibration for the measurement path for gain 24 Revision 1.2, 08-Junel-06 41 100 -25 -50 -75 linearity deviation cubic fit -100 50 75 100 125 150 175 temperature in deg C www.austriamicrosystems.com Page 13 of ...
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... The TC-value of the output (total measurement path) for G24 can be trimmed to a minimum value by selecting the best setting of the TRIMBTC subregister of the TRR register (see 7.5.7). A factory calibration is done for the amplifier offset (TRIMA). This data is stored in the ZZR register. ZZR-register mapping is given in 8.6.2 Revision 1.2, 08-Junel-06 41 output/digits 30 000 30 000 30 000 30 000 30 000 www.austriamicrosystems.com Page 14 of ...
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... Modes of operation The AS8500 can run in different operation modes, which are selected and activated via the serial interface. Detailed description: Mode 0: MZL In power-on reset sequence, which is initiated by the on-chip power-on reset circuit whenever the power is connected , the registers are loaded from the Zener-Zap memory ...
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... All internal functions are controlled by the contents of these registers which can be reloaded via the serial SDI interface at any time. The AS8500 contains the following registers: REGISTER ADDRESS ...
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... AS8500 - Data Sheet 7.5.1 OPM operation mode register ( 4 bits ) no. Bit mo3 mo2 0 default 0 1) This register has been described in detail under 7.4 7.5.2 CRG general configuration register ( 28 bits ) no. CRG bits 27-22 21-11 0 CRS CRI subregister CRS: Sequence length, dechop and chop ( 6 bits ) Nr ...
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... AS8500 - Data Sheet Current source setting bits (5 bits) Nr. Current [uA … … 31 248 subregister CRV: Voltage configuration (4 bits ) Nr. Bits 3 0 CRV bit M15 names 1 Defaults 0 2 channel VBAT- VBAT-ETS RSHL differential Notes: 1) This register defines the connection of the analog voltage- bus to the input-PINs and to the A/D converter ...
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... AS8500 - Data Sheet subregister CRU: calibration constant selection for voltage path ( 3 bits) in registers CRA,CRB Nr. Calibration const CAU0 1 CAU1 2 CAU2 3 CAU3 4 CAU4 5 CAU5 6 1548 7 1548 subregister CRM: measurement path for registers CRA,CRB Nr. Bits 13 12 CRA bit M5 M4 names 1 Defaults Notes: 1) these bits define the inner part of the voltage path settings ...
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... AS8500 - Data Sheet subregister MM: chopping ratio bit, Registers CRA, CRB Nr Notes: 1) For c=0 and d=0 , chopping and dechopping is switched off and every cycle is active regardless of mm, i.e. the sampling frequenzy is higher by a factor of 4 subregister CRN: averaging bits ( 4 bits), registers CRA,CRB Nr ...
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... AS8500 - Data Sheet 7.5.5 ZZR Zener-Zap register (188 bits ): For the AS8500 the zener zap registers are set to a predefined default value exception the TRIMA bits in the ZTR subregister is factory adjusted for minimum amplifier offset to ensure optimum linearity over input range. ...
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... AS8500 - Data Sheet Calibration constant selection truth table Nr. cu2 cu1 cu0 Notes: 1) CGIx calibration constants are selected when M1=1 according to selected gain 2) CGUx calibration constants are selected when M1=0 according to bits cu2 to cu0 defined via SDI in CRA and/or CRB registers. subregister ZTC: These bits are spare bits and can be used on special request (e ...
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... AS8501). At power-up sequence the Zener-Zap subregister ZCL default setting is copied into the CAR register. The register can be read or written in mode 8 via the SDI bus at any time. In particular for the AS8500, which is not factory calibrated it is intended to overwrite the default setting with external data defined by the user. ...
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... AS8500 - Data Sheet subregister TRIMA The offset of the PGA is factory trimmed to a mimimum absolute value to guarantee the full dynamic range with all gain settings. change of amplifier offset with TRIMA bits Nr. trimas trima3 Notes: Uos is the input offset voltage TRIMA = 00000 1) Every step of TRIMA settings brings $offset=1.34 mV change in absolute value of the input offset voltage. ...
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... AS8500 - Data Sheet TRIMBV=16+int(-(Uam-1.232)/0.0051) for Uam below the ideal value. subregister TRIMBTC change of reference voltage Uo and TC-value with TRIMBTC bits Nr. trimbtcs trimbtc3 trimbtc2 Notes the reference voltage in mV and TCo is the TC value in ppm/K at TRIMBV = 00000 1) Every step of TRIMBTC settings brings $ 2) S=12 ...
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... Digital interface description The digital interface of the AS8500 consists of two input pins (CLK and SCLK) and two I/O pins (INTN and SDAT). The SCLK and SDAT pins are used as universal serial data interface (SDI). SDI operates only if external clock signal (CLK) is running. ...
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... AS8500 - Data Sheet The trailing edge of INTN signals the start of a new measurement. INTN available i-2 results on SDI Figure 5: INTN pin in modes 1 and 2 The determination of Tcnv and Tres from the parameter settings is: Tcnv % R1/(fovs*2) 8.3 SDI bus operation SDI bus is a 2-line bi-directional interface between one master and one slave unit. Typically the master unit is a microcontroller with software- implemented SDI protocol ...
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... AS8500 - Data Sheet The slave unit drives the sdat signal only in master-read data condition. In all other cases the slave sdat pin is in high-impedance state. During data transfer in read condition the internal AD-conversion in continuing but the data in the MSR-register is not updated and the output of the INTN signal is suppressed ...
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... AS8500 - Data Sheet 7 TRR 8 THR 8.5 SDI bus timing Timing definitions for SDI bus are based on software-implemented master unit protocol MDE sclk (uP) master sdat (uP) slave sdat (ASIC) strobe ASSP Figure 8: SDI Bus timing Revision 1.2, 08-Junel-06 41 trimming register alarm or wake-up threshold register ...
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... AS8500 - Data Sheet SDI bus timing Nr. PARAMETER 0 SCLK pulse width 1 SCLK low 2 Master SDAT exception after SCLK 3 Master SDAT valid before/after SCLK 4 Slave SDAT not valid after SCLK 5 Master 3-state ON/OFF 6 Slave 3-state ON/OFF 7 Bus condition detection disabled in slave unit Notes: ...
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... AS8500 - Data Sheet Cell index 8 trimc0 Purpose trimc1 ZTR ZZR field ZTR 178 ZZR bit 179 Cell index 16 17 trimbv2 Purpose trimbv3 ZTR ZZR field ZTR 170 ZZR bit 171 Cell index 24 25 cgi1_10 Purpose trimbtc0 ZCL ZZR field ZTR 162 ...
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... AS8500 - Data Sheet Cell index 72 73 Purpose cau0_7 cau0_6 ZZR field ZCL ZCL ZZR bit 115 114 Cell index 80 81 cau1_9 Purpose cau1_10 ZZR field ZCL ZCL ZZR bit 107 106 Cell index 88 89 Purpose cau1_2 cau1_1 ZZR field ZCL ZCL ...
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... AS8500 - Data Sheet Cell index 136 137 Purpose tcu1_7 tcu1_6 ZZR field ZTC ZTC ZZR bit 51 50 Cell index 144 145 Purpose tcu0_8 tcu0_7 ZZR field ZTC ZTC ZZR bit 43 42 Cell index 152 153 Purpose tcu0_0 trt0_10 ZZR field ZTC ...
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... AS8500 - Data Sheet 8.6.2 Stored ZZR-register mapping ZZR subreg bitno in subregister 10 9 msb ZLO ZTR TRIMC TRIMA TRIMBV TRIMBTC ZCL CGI1 1 1 CGI2 1 1 CGI3 1 1 CGI4 0 0 CAU0 1 1 CAU1 1 1 CAU2 1 1 CAU3 1 1 CAU4 1 1 CAU5 1 1 ZTC ...
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... In most applications the input resistor or input divider is low ohmic (i.e. below 10 kOhms) which mean that the noise voltage produced by the input current noise is negligible compared to the input voltage noise. The input noise density (En) of the AS8500 is with only 35 nV/sqr(Hz) extremely low. ...
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... Shielding, guarding In many applications it is difficult to gain full benefit from the AS8500 performance since a number of external error sources can disturb the measurement. To achieve the maximum performance the design engineer has to take care specially of the layout of the PC-board and the sense connections to the external components ...
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... Typical performance characteristics Revision 1.2, 08-Junel-06 41 www.austriamicrosystems.com Page 37 of ...
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... Revision 1.2, 08-Junel-06 41 www.austriamicrosystems.com Page 38 of ...
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... Thermal Resistance junction / ambient.: 66 K/W (typ.) in still air 11 Revision History Revision Date 1.0 Feb.10, 2006 1.1 March 23, 2006 1.2 June 2006 12 Ordering Information Delivery: Tape and Reel (1 reel = 1500 devices) = MOQ Order AS8500 Revision 1.2, 08-Junel-06 41 Description Initial Revision TRIMA 8.6.2, R thJA Remove preliminary www.austriamicrosystems.com Page 39 of ...
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... Fax: +39 02 4585 773 austriamicrosystems France S.A.R.L. 124, Avenue de Paris F-94300 Vincennes, France Phone: + Fax: + austriamicrosystems Switzerland AG Rietstrasse 4 CH 8640 Rapperswil, Switzerland Phone: +41 55 220 9008 Fax: +41 55 220 9001 austriamicrosystems UK, Ltd. 88, Barkham Ride, Finchampstead, Wokingham Berkshire RG40 4ET, United Kingdom ...
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... To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. However, austriamicrosystems shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein ...