LTC1290CIJ Linear Technology, LTC1290CIJ Datasheet - Page 13

• Manufacturer Part Number: LTC1290CIJ
• Description: 12-BIT SERIAL I/O ADC W/8 CH MUX
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS), ADCr

Specifications of LTC1290CIJ

• Resolution (bits): 12 b
• Sampling Rate (per Second): 50k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Dual ±
• Voltage - Supply: ±5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MSB-First/LSB-First Format (MSBF)
The output data of the LTC1290 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB
first output data the input word clocked to the LTC1290
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
word clocked to the LTC1290 should always contain a zero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
Word Length (WL1, WL0) and Power Shutdown
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1290. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
The WL1 and WL0 bits in a given D
length of the present, not the next, D
WL0 are never “don’t cares” and must be set for the
correct D
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous conversion result will be clocked
out as a 10 bit word so a “dummy” conversion is required
before powering down the LTC1290. Conversions are
ACLK
D
A
OUT
CS
PPLICATI
OUT
MSBF
word length even when a “dummy” D
0
1
HI-Z
Low CS Recognized Internally
O
U
S
I FOR ATIO
U
OUTPUT FORMAT
W
IN
OUT
MSB First
LSB First
VALID OUTPUT
word control the
word. WL1 and
U
IN
word
LTC1290 • AI06
ACLK
D
resumed once CS goes low or an SCLK is applied, if CS is
already low.
Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1290 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
one ACLK cycle. After a change of state on the CS input, the
LTC1290 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the D
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1290 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
D
the data transfer can begin as normal.
OUT
OUT
CS
line will become active with the first output bit. Then
WL1
0
0
1
1
VALID OUTPUT
High CS Recognized Internally
WL0
OUT
0
1
0
1
line becoming active (leaving the
OUTPUT WORD LENGTH
Power Shutdown
HI-Z
12-Bits
16-Bits
8-Bits
LTC1290
13
LTC1290 • AI07
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