AD5290YRMZ10 Analog Devices Inc, AD5290YRMZ10 Datasheet - Page 17

• Manufacturer Part Number: AD5290YRMZ10
• Description: IC DGTL POT 10K 256POS 10MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5290YRMZ10

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 30 V, ±4.5 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 10K
• End To End Resistance: 10kohm
• No. Of Steps: 256
• Resistance Tolerance: ± 30%
• Supply Voltage Range: ± 10V To ± 15V
• Control Interface: Serial, SPI
• No. Of Pots: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5290EBZ - BOARD EVAL FOR AD5290
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ESD PROTECTION
All digital inputs are protected with a series input resistor and
a Zener ESD structure, as shown in Figure 30. These structures
apply to digital input pins, Pin CS , Pin CLK, Pin SDI, and
Pin SDO.
All analog terminals are also protected by Zener ESD protection
diodes, as shown in Figure 31.
TERMINAL VOLTAGE OPERATING RANGE
The AD5290 V
conditions for proper 3-terminal digital potentiometer opera-
tion. The AD5290 can operate in single supply from +4.5 V to
+33 V or dual supply from ±4.5 V to ±16.5 V. The AD5290 is
functional at low supply voltages such as 4.5 V, but the
performance parameters are not guaranteed.
The voltages present on Terminal A, Terminal B, and Terminal W
that are more positive than V
clamped by the internal forward-biased diodes (Figure 31).
Figure 31. Equivalent ESD Protection Analog Pins
Figure 30. Equivalent ESD Protection Circuit
DD
and V
GND
SS
340
power supplies define the boundary
DD
LOGIC
or more negative than V
V
V
A
W
B
SS
DD
SS
are
Rev. B | Page 17 of 20
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W
(Figure 31), it is important to power V
any voltage to Terminal A, Terminal B, and Terminal W.
Otherwise, the diodes are forward-biased such that V
are powered unintentionally and affect the system. Similarly,
V
sequence is as follows: GND, V
V
inputs is not important, as long as they are powered after
V
LAYOUT AND POWER SUPPLY BIASING
It is good practice to use a compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR),
1 μF to 10 μF tantalum or electrolytic capacitors, should be
applied at the supplies to minimize any transient disturbance
and to filter low frequency ripple. Figure 32 illustrates the basic
supply-bypassing configuration for the AD5290.
The ground pin of the AD5290 is a digital ground reference.
To minimize the digital ground bounce, the AD5290 digital
ground terminal should be joined remotely to the analog
ground (Figure 32).
DD
A
DD
/V
/V
/V
B
/V
SS
SS
.
should be powered down last. The ideal power-up
W
. The order of powering V
V
V
DD
SS
C3
C4
Figure 32. Power Supply Bypassing
+
10F
+ C2
10F
C1
0.1F
0.1F
DD
, V
V
V
SS
A
DD
SS
, V
, digital inputs, and
AD5290
DD
B
/V
, V
GND
SS
W
before applying
, and the digital
AD5290
DD
/V
SS