ISL90842UIV1427Z-TK Intersil, ISL90842UIV1427Z-TK Datasheet - Page 4

• Manufacturer Part Number: ISL90842UIV1427Z-TK
• Description: IC POT DGTL QUAD 50K OHM 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL90842UIV1427Z-TK

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL90842UIV1427Z-TKTR

Operating Specifications
SERIAL INTERFACE SPECS
Cb (Note 8) Capacitive loading of SDA or SCL
Hysteresis
SYMBOL
(Note 8)
(Note 8)
(Note 8)
(Note 8)
(Note 8)
(Note 8)
(Note 8)
t
t
(Note 8)
(Note 8)
(Note 8)
(Note 8)
t
t
t
t
SU:STO
HD:STO
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
t
Cpin
f
t
V
HIGH
LOW
Rpu
DCP
V
BUF
t
V
SCL
t
t
DH
AA
t
t
OL
IN
R
IH
F
IL
DCP wiper response time
A1, A0, SDA, and SCL input buffer
LOW voltage
A1, A0, SDA, and SCL input buffer
HIGH voltage
SDA and SCL input buffer hysteresis
SDA output buffer LOW voltage,
sinking 4mA
A1, A0, SDA, and SCL pin
capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
Input data setup time
Input data hold time
STOP condition hold time
STOP condition hold time for read, or
volatile only write
Output data hold time
SDA and SCL rise time
SDA and SCL fall time
SDA and SCL bus pull-up resistor off-
chip
PARAMETER
4
Over the recommended operating conditions unless otherwise specified. (Continued)
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
SCL falling edge of last bit of DCP data byte
to wiper change
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
during the following START condition
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge; both
crossing 70% of V
From SDA falling edge crossing 30% of V
to SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
to SDA entering the 30% to 70% of V
window
From SCL rising edge crossing 70% of V
to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window
Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
CC
ISL90842
TEST CONDITIONS
CC
CC
CC
CC
CC
CC
CC
during a STOP
R
crossing
crossing
and t
CC
window
CC
F
CC
CC
CC
CC
CC
, until
CC
CC
CC
CC
CC
,
,
0.7*V
0.1 * Cb
0.1 * Cb
0.05*
1300
1300
V
20 +
20 +
MIN
-0.3
600
600
600
100
600
600
10
CC
0
0
0
1
CC
(NOTE 1)
TYP
V
0.3*V
CC
MAX
400
900
250
250
400
0.4
10
50
1
+0.3
CC
January 16, 2006
UNIT
kHz
FN8096.1
kΩ
pF
pF
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V