MCP4162-503E/MS Microchip Technology, MCP4162-503E/MS Datasheet - Page 33

IC POT DGTL SNGL 50K RHEO 8MSOP

MCP4162-503E/MS

Manufacturer Part Number
MCP4162-503E/MS
Description
IC POT DGTL SNGL 50K RHEO 8MSOP
Manufacturer
Microchip Technology
Datasheets

Specifications of MCP4162-503E/MS

Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Taps
257
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Resistance In Ohms
50K
Number Of Pots
Single
Taps Per Pot
256
Resistance
50 KOhms
Wiper Memory
Non Volatile
Digital Interface
Serial (4-Wire, SPI)
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Supply Current
550 uA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP4162-503E/MS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
4.2.2.2
This register contains 8 control bits. Four bits are for
Wiper 0, and four bits are for Wiper 1.
describes each bit of the TCON register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal connec-
tion (A, B and W) can be individually connected/discon-
nected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
REGISTER 4-2:
© 2007 Microchip Technology Inc.
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
R-1
D8
2:
The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the
inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the
state of the TCON bits.
These bits do not affect the wiper register values.
Terminal Control (TCON) Register
D8: Reserved. Forced to “1”
R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 1 is forced to the hardware pin “shutdown” configuration
R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1 = P1A pin is connected to the Resistor 1 Network
0 = P1A pin is disconnected from the Resistor 1 Network
R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1 = P1W pin is connected to the Resistor 1 Network
0 = P1W pin is disconnected from the Resistor 1 Network
R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1 = P1B pin is connected to the Resistor 1 Network
0 = P1B pin is disconnected from the Resistor 1 Network
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
R1HW
R/W-1
TCON BITS
W = Writable bit
‘1’ = Bit is set
R/W-1
R1A
(1, 2)
Register 4-2
R/W-1
R1W
MCP414X/416X/424X/426X
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
R1B
The value that is written to this register will appear on
the resistor network terminals when the serial com-
mand has completed.
When the WL1 bit is enabled, writes to the TCON reg-
ister bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON reg-
ister bits R0HW, R0A, R0W, and R0B are inhibited.
On a POR/BOR this register is loaded with 1FFh
(9-bits), for all terminals connected. The Host Control-
ler needs to detect the POR/BOR event and then
update the Volatile TCON register value.
R0HW
R/W-1
x = Bit is unknown
R/W-1
R0A
R/W-1
R0W
DS22059A-page 33
R/W-1
R0B
bit 0

Related parts for MCP4162-503E/MS