ISL22316UFU10Z-TK Intersil, ISL22316UFU10Z-TK Datasheet - Page 11

• Manufacturer Part Number: ISL22316UFU10Z-TK
• Description: IC POT DGTL 128TP LN LP 10-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22316UFU10Z-TK

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 80 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

non-volatile register (IVR) at address 0, contain initial wiper
position and volatile registers (WR) contain current wiper
position.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically AND with SHDN pin. When this bit is 0, DCP
is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register
to 0. The truth table for Shutdown mode is in Table 3.
I
The ISL22316 supports an I
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22316
operates as a slave device in all applications.
2
ADDRESS
C Serial Interface
VOL
SHDN pin
2
1
0
High
High
TABLE 2. ACCESS CONTROL REGISTER (ACR)
Low
Low
SHDN
NON-VOLATILE
TABLE 1. MEMORY MAP
WIP
SHDN bit
IVR
—
1
1
0
0
TABLE 3.
2
11
C bidirectional bus oriented
0
Reserved
0
Normal operation
0
Shutdown
Shutdown
Shutdown
VOLATILE
Mode
ACR
WR
0
0
ISL22316
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22316, the SDA pin
is in the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22316 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22316 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22316 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write bit. Its value is
“1” for a Read operation, and “0” for a Write operation
(see Table 4).
(MSB)
0
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
TABLE 4. IDENTIFICATION BYTE FORMAT
1
Logic values at pins A1 and A0 respectively
0
1
2
C interface is conducted by
0
A1
September 1, 2009
A0
FN6186.2
(LSB)
R/W