ISL22317UFRTZ Intersil, ISL22317UFRTZ Datasheet - Page 2

• Manufacturer Part Number: ISL22317UFRTZ
• Description: IC POT DGTL 128TP LN LP 10-TDFN
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22317UFRTZ

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TDFN Exposed Pad
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Temperature Coefficient: -

Pinout
Ordering Information
NOTES:
Block Diagram
ISL22317TFRTZ
ISL22317UFRTZ
ISL22317WFRTZ
1. Add “-TK” suffix for tape and reel. Please refer to
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL22317. For more information on MSL please see techbrief
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
TB363.
PART NUMBER
(Notes 1, 2, 3)
REF_A
REF_B
SDA
SCL
A1
for U and T options
External Resistor
or 50kΩ 0.5%
for W option,
1
2
3
4
5
respectively
10kΩ 0.5%
(10 LD TDFN)
TOP VIEW
ISL22317
317T
317U
317W
R
2
MARKING
REF
PART
REF_A
REF_B
SDA
SCL
10
A1
9
8
7
6
VCC
RH
RW
RL
GND
TB347
RESISTANCE OPTION
for details on reel specifications.
INTERFACE,
POWER-UP,
(kΩ)
100
CONTROL
50
10
EEPROM
ISL22317
LOGIC
AND
Pin Descriptions
*PCB thermal land for QFN/TDFN EPAD should be connected to
GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
TDFN
PIN #
10
GND
1
2
3
4
5
6
7
8
9
VCC
TEMP. RANGE
SYMBOL
-40 to +125
-40 to +125
-40 to +125
REF_A
REF_B
EPAD*
GND
SDA
VCC
SCL
RW
RH
RL
A1
(°C)
Open drain I
Open drain Serial data I/O for the I
Device address input for the I
Terminal A for an external reference resistor
Terminal B for an external reference resistor
Device ground pin
“Low” terminal of DCP
“Wiper” terminal of DCP
“High” terminal of DCP
Power supply pin
Exposed Die Pad internally connected to
GND
10 Ld TDFN
10 Ld TDFN
10 Ld TDFN
PACKAGE
2
(Pb-free)
C interface clock input
DESCRIPTION
RW
RL
RH
2
L10.3x3B
L10.3x3B
L10.3x3B
C interface
2
DWG. #
C interface
PKG.
April 15, 2010
FN6912.1