BU2507FV-E2 Rohm Semiconductor, BU2507FV-E2 Datasheet - Page 5

• Manufacturer Part Number: BU2507FV-E2
• Description: IC DAC 10BIT 6-CHAN SSOP-B14
• Manufacturer: Rohm Semiconductor

Specifications of BU2507FV-E2

• Data Interface: Serial
• Settling Time: 7µs
• Number Of Bits: 10
• Number Of Converters: 6
• Voltage Supply Source: Single Supply
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SSOP
• Resolution (bits): 10bit
• Sampling Rate: 10MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Current: 850µA
• Digital Ic Case Style: SSOP
• No. Of: RoHS Compliant
• Resolution: 10 bit
• Interface Type: Serial (3-Wire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 30 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: BU2507FV-E2; BU2507FV-E2TR

●Command Sending
© 2009 RzOHM Co., Ltd. All rights reserved.
BU2508FV,BU2507FV
www.rohm.com
1) In the case of BU2507FV
2) In the case of BU2508FV
DA出力
DA出力
CLK
CLK
LD
(1) Data format [data : LSB first]
(2) Data timing diagram
(1) Data format [Data: LSB first ]
(2) Data timing diagram
DI
LD
output
DI
output
D13
D13
Last
MSB
Last
MSB
：
Ｄ13 Ｄ12
0
0
0
0
1
1
Ｄ13 Ｄ12
0
1
0
1
0
1
:
LSB
LSB
Ｄ0
D12
Ｄ0
D12
Ｄ11 Ｄ10
Ｄ11 Ｄ10
：
For D/A converter output setting
0
0
0
0
1
1
0
0
1
1
1
1
For D/A converter output setting
:
Ｄ／Ａｺﾝﾊﾞｰﾀ出力設定用
Ｄ／Ａｺﾝﾊﾞｰﾀ出力設定用
Ｄ1
Ｄ1
D11
D11
Ｄ9
Ｄ9
：
Ｄ2
0
0
0
0
1
1
0
0
0
0
1
1
:
Ｄ2
Ｄ8
Ｄ8
Ｄ3
Ｄ3
Ｄ7
Ｄ7
D10
D10
：
0
0
0
0
1
1
0
0
0
0
1
1
:
Ｄ6
Ｄ6
Ｄ5
Ｄ5
D9
D9
：
0
0
0
0
1
1
0
0
0
0
1
1
Ｄ11
:
Ｄ11
Ｄ4
Ｄ4
Ｄ12
Ｄ12
Ｄ3
Ｄ3
D8
D8
：
For address selection
For address selection
0
0
0
0
1
1
0
0
0
0
1
1
:
ｱﾄﾞﾚｽ選択用
ｱﾄﾞﾚｽ選択用
MSB
Ｄ13
Ｄ2
Ｄ2
MSB
Ｄ13
D7
D7
Ｄ1
Ｄ1
：
0
0
0
0
1
1
0
0
0
0
1
1
:
5/8
First
LSB
First
LSB
Ｄ0
Ｄ0
D6
D6
：
0
0
0
0
1
1
0
0
0
0
1
1
:
Ｄ3
D5
D3
D5
：
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
:
Ｄ2
D4
D4
D2
：
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
:
D/A output (VrefH=VDD, VrefL=VSS)
VrefL
VrefL
(VrefH-VrefL)/1024×1+VrefL
(VrefH-VrefL)/1024×2+VrefL
(VrefH-VrefL)/1024×3+VrefL
(VrefH-VrefL)/1024×1022+VrefL
(VrefH-VrefL)/1024×1023+VrefL
(VrefH-VrefL)/1024×1+VrefL
(VrefH-VrefL)/1024×2+VrefL
(VrefH-VrefL)/1024×3+VrefL
(VrefH-VrefL)/1024×1022+VrefL
(VrefH-VrefL)/1024×1023+VrefL
Ｄ1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D/A output（VrefH=VDD,
Ｄ0
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VrefL=VSS）
Technical Note
2009.06 - Rev.A
Address selection
Address selection
:
:
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
Inconsequential
AO1 selection
AO2 selection
AO3 selection
AO4 selection
AO5 selection
AO6 selection
AO1 selection
AO2 selection
AO3 selection
AO4 selection
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care