AD9717BCPZ Analog Devices Inc, AD9717BCPZ Datasheet
AD9717BCPZ
Specifications of AD9717BCPZ
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AD9717BCPZ Summary of contents
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FEATURES Power dissipation @ 3 output MSPS 125 MSPS Sleep mode: < 3.3 V Supply voltage: 1 3.3 V SFDR to Nyquist 84 dBc @ 1 ...
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AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 7 AC Specifications ...
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REVISION HISTORY 3/09—Rev Rev. A Changes to Figure 1 ........................................................................... 4 Changed DVDD = 3 DVDD = 1.8 V, Table 1 Conditions ............................................................................ 5 Changes to Table 1 ............................................................................ 5 Changed DVDD = 3 ...
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AD9714/AD9715/AD9716/AD9717 FUNCTIONAL BLOCK DIAGRAM DB11 DB10 DB9 DB8 DVDDIO DVSS DVDD 1.8V LDO DB7 DB6 DB5 1V SPI QR INTERFACE SET 16kΩ 10kΩ I REF 100µA BAND AUX1DAC GAP 1 INTO 2 INTERLEAVED AUX2DAC I DATA DATA INTERFACE Q DATA ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3 MIN MAX otherwise noted. Table 1. AD9714 Parameter Min Typ RESOLUTION 8 ACCURACY, AVDD = DVDDIO ...
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AD9714/AD9715/AD9716/AD9717 AD9714 Parameter Min REFERENCE INPUT Voltage Compliance AVDD = 3.3 V 0.1 AVDD = 1.8 V 0.1 Input Resistance External Reference Mode DAC MATCHING Gain Matching −1 ANALOG SUPPLY VOLTAGES AVDD 1.7 CVDD 1.7 DIGITAL SUPPLY VOLTAGES DVDD 1.7 ...
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DIGITAL SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3 MIN MAX otherwise noted. Table 2. Parameter DAC CLOCK INPUT (CLKIN Maximum Clock ...
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AD9714/AD9715/AD9716/AD9717 AC SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3 MIN MAX otherwise noted. Table 3. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR 125 MSPS, f ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS DVDD to DVSS AVSS to DVSS, CVSS DVSS to AVSS, CVSS CVSS to AVSS, DVSS REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS QOUTP, QOUTN, IOUTP, IOUTN, RLQP, ...
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AD9714/AD9715/AD9716/AD9717 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 7. AD9714 Pin Function Descriptions Pin No. Mnemonic Description DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD ...
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Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IR on-chip IR disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the ...
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AD9714/AD9715/AD9716/AD9717 Table 8. AD9715 Pin Function Descriptions Pin No. Mnemonic Description DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 ...
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Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IR on-chip IR disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the ...
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AD9714/AD9715/AD9716/AD9717 Table 9. AD9716 Pin Function Descriptions Pin No. Mnemonic Description DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 ...
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Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IR on-chip IR disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the ...
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AD9714/AD9715/AD9716/AD9717 Table 10. AD9717 Pin Function Descriptions Pin No. Mnemonic Description DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1 3.3 V Nominal). 6 DVSS Digital Common. 7 DVDD Digital Core Supply Voltage (1.8 ...
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Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IR on-chip IR disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor (see the ...
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AD9714/AD9715/AD9716/AD9717 TYPICAL PERFORMANCE CHARACTERISTICS mA, maximum sample rate, unless otherwise noted. DVDD is always at 1.8 V. xOUTFS 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 6. ...
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CODE Figure 12. AD9717 Precalibration DNL at 3.3 V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 ...
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AD9714/AD9715/AD9716/AD9717 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 CODE Figure 18. AD9716 Precalibration INL at 3.3 V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 1536 2048 2560 ...
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CODE Figure 24. AD9715 Precalibration DNL at 1.8 V 0.13 0.08 0.03 –0.02 –0.07 –0.12 0 128 256 384 512 640 768 CODE Figure 25. AD9715 Precalibration ...
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AD9714/AD9715/AD9716/AD9717 0.025 0.020 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 –0.025 112 128 144 160 CODE Figure 30. AD9714 Precalibration INL at 1.8 V 0.025 0.020 0.015 0.010 0.005 0 –0.005 –0.010 ...
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CODE Figure 36. AD9714 Precalibration DNL at 3.3 V –126 AD9714 –132 –138 AD9715 –144 AD9716 AD9717 –150 ...
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AD9714/AD9715/AD9716/AD9717 –130 –133 –136 –139 1.8V, 1mA –142 1.8V, 2mA –145 –148 –151 –154 –157 (MHz) OUT Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.8 V –10 –20 –30 ...
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OUT Figure 48. AD9717 IMD at Three Temperatures, 1 –3dB –6dB 70 64 0dB ...
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AD9714/AD9715/AD9716/AD9717 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 START 1MHz 1.5MHz/DIV Figure 54. AD9717 Single-Tone Spectrum, 1 AD9717 AD9716 80 AD9715 AD9714 ...
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IN Figure 60. SFDR at Three Digital Input Levels vs 1mA 66 2mA ...
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AD9714/AD9715/AD9716/AD9717 –60 1mA POSTCAL –65 2mA POSTCAL –70 2mA PRECAL – (MHz) OUT Figure 66. AD9717 One-Carrier W-CDMA First ACLR, 1.8 V –60 –65 1mA POSTCAL 2mA PRECAL –70 2mA POSTCAL – (MHz) OUT ...
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AC-COUPLED: UNSPECIFIED BELOW 20MHz CENTER 22.90MHz SPAN 38.84MHz VBW 300kHz RES BW 30kHz SWEEP 126ms (601pts) TOTAL CARRIER POWER –23.08dBm/7.87420MHz REF CARRIER POWER –25.84dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER FREQ BW dBc dBm 1. –25.84dBm 5.000MHz ...
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AD9714/AD9715/AD9716/AD9717 –55 1mA PRECAL –60 1mA POSTCAL 2mA PRECAL –65 2mA POSTCAL – (MHz) OUT Figure 78. AD9717 Two-Carrier W-CDMA Third ACLR, 1.8 V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 128 ...
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TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL ...
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AD9714/AD9715/AD9716/AD9717 THEORY OF OPERATION DB11 DB10 DB9 DB8 DVDDIO DVSS DVDD 1.8V LDO DB7 DB6 DB5 Figure 84 shows a simplified block diagram of the AD9714/ AD9715/AD9716/AD9717 that consists of two DACs, digital control logic, and a full-scale output current ...
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SERIAL PERIPHERAL INTERFACE (SPI) The serial port of the AD9714/AD9715/AD9716/AD9717 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchron- ous transfer formats, including both ...
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AD9714/AD9715/AD9716/AD9717 MSB/LSB TRANSFERS The serial port of the AD9714/AD9715/AD9716/AD9717 can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is ...
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SPI REGISTER MAP Table 13. Name Addr Default SPI Control 0x00 0x00 Power-Down 0x01 0x40 Data Control 0x02 0x34 I DAC Gain 0x03 0x00 IRSET 0x04 0x00 IRCML 0x05 0x00 Q DAC Gain 0x06 0x00 QRSET 0x07 0x00 QRCML 0x08 ...
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AD9714/AD9715/AD9716/AD9717 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register Address Bit Name SPI Control 0x00 6 LSBFIRST 5 Reset 4 LNGINS Power-Down 0x01 7 LDOOFF 6 LDOSTAT ...
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Register Address Bit Name IRSET 0x04 7 IRSETEN 5:0 IRSET[5:0] IRCML 0x05 7 IRCMLEN 5:0 IRCML[5:0] Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] QRSET 0x07 7 QRSETEN 5:0 QRSET[5:0] QRCML 0x08 7 QRCMLEN 5:0 QRCML[5:0] AUXDAC Q 0x09 7:0 QAUXDAC[7:0] ...
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AD9714/AD9715/AD9716/AD9717 Register Address Bit Name AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUX CTLI 0x0C 7 IAUXEN 6:5 IAUXRNG[1:0] 4:2 IAUXOFS[2:0] 1:0 IAUXDAC[9:8] Reference 0x0D 5:0 RREF[5:0] Resistor Cal Control 0x0E 7 PRELDQ 6 PRELDI 5 CALSELQ 4 CALSELI 3 CALCLK 2:0 ...
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Register Address Bit Name Memory R/W 0x12 7 CALRSTQ 6 CALRSTI 4 CALEN 3 SMEMWR 2 SMEMRD 1 UNCALQ 0 UNCALI CLKMODE 0x14 7:6 CLKMODEQ[1:0] 4 Searching 3 Reacquire 2 CLKMODEN 1:0 CLKMODEI[1:0] Version 0x1F 7:0 Version[7:0] AD9714/AD9715/AD9716/AD9717 Description 0 ...
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AD9714/AD9715/AD9716/AD9717 DIGITAL INTERFACE OPERATION Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0), where for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) ...
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OR D-FF 0 DB[n:0] (INPUT) DCLKIO-INT NOTES: 1. DB[n:0], WHERE FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing DIGITAL DATA LATCHING AND ...
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AD9714/AD9715/AD9716/AD9717 Table 15. Timer Register List Bit Name Description CLKMODEQ[1:0] Q data path retimer clock selected output. Valid after the searching bit goes low. Searching High indicates that the internal data path retimer is searching for the clock relationship (DAC ...
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REFERENCE OPERATION The AD9714/AD9715/AD9716/AD9717 contain an internal 1.0 V band gap reference. The internal reference can be disabled by setting Bit 0 (EXTREF) of the power-down register (Address 0x01) through the SPI interface. To use the internal reference, decouple the ...
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AD9714/AD9715/AD9716/AD9717 DAC TRANSFER FUNCTION The AD9714/AD9715/AD9716/AD9717 provide two differen- tial current outputs, IOUTP/IOUTN and QOUTP/QOUTN. IOUTP and QOUTP provide a near full-scale current output when all bits are high (that is, DAC CODE = 2 xOUTFS where N ...
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SELF-CALIBRATION The AD9714/AD9715/AD9716/AD9717 have a self-calibration feature that improves the DNL of the device. Performing a self- calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above ...
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AD9714/AD9715/AD9716/AD9717 COARSE GAIN ADJUSTMENT Option 1 A coarse full-scale output current adjustment can be achieved using the lower six bits in Register 0x0D. This adds or subtracts up to 20% from the band gap voltage on Pin 34 (REFIO), and ...
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USING THE INTERNAL TERMINATION RESISTORS The AD9717/AD9716/AD9715/AD9714 have four 500 Ω termination internal resistors (two for each DAC output). To use these resistors to convert the DAC output current to a voltage, connect each DAC output pin to the adjacent ...
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AD9714/AD9715/AD9716/AD9717 APPLICATIONS INFORMATION OUTPUT CONFIGURATIONS The following sections illustrate some typical output confi- gurations for the AD9714/AD9715/AD9716/AD9717. Unless otherwise noted assumed that I xOUTFS 2 mA. For applications requiring the optimum dynamic perfor- mance, a differential output configuration ...
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DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP A dual op amp (see the circuit shown in Figure 105) can be used in a differential version of the single-ended buffer shown in Figure 104. The same RC network is used to ...
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AD9714/AD9715/AD9716/AD9717 Two registers are assigned to each DAC with 10 bits for the actual DAC current to be generated, a 3-bit offset (and gain) adjust- ment, a 2-bit current range adjustment, and an enable/disable bit. Setting the QAUXOFS (Register 0x0A, ...
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Note that LO feedthrough compensation is independent of phase compensation. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. ...
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AD9714/AD9715/AD9716/AD9717 MODIFYING THE EVALUATION BOARD TO USE THE ADL5370 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/ AD9716/AD9717 and the ADL5370 provide an easy-to- interface DAC/modulator combination that can be easily characterized ...
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EVALUATION BOARD SHEMATICS AND ARTWORK SCHEMATICS RC0603 CC0603 RC0603 RC0603 CC0603 CC0603 Figure 112. Power Supplies and Filters Rev Page AD9714/AD9715/AD9716/AD9717 07265-184 RC0603 CC0603 RC0603 CC0603 ...
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AD9714/AD9715/AD9716/AD9717 DNP RNETCTS743-8 RP1 FEMALE ANGLE RIGHT HEADER Figure 113. Digital Inputs Rev Page 07265-185 RNETCTS743 ...
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RC0402 RC0402 RC0402 RC0402 RC0402 CC0402 CC0402 RC0402 RC0402 Figure 114. Clock Input and DUT AD9714/AD9715/AD9716/AD9717 RC0603 R7 Rev Page 07265-186 ...
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AD9714/AD9715/AD9716/AD9717 RC0603 RC0603 RC0603 RC0603 RC0603 CC0402 RC0603 RC0603 RC0603 RC0603 Figure 115. IOUT Network and FSADJ1 Rev Page 07265-187 CC0805 CC0603 CC0603 RC0603 JP12 RC0603 RC0603 RC0805 JP9 ERA6Y ERA6YEB323V, RC0805 JP8 ERA6Y ERA6YEB323V, ...
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RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 AD9714/AD9715/AD9716/AD9717 RC0603 RC0603 Figure 116. QOUT Network and FSADJ2 Rev Page 07265-188 RC0603 JP77 RC0603 RC0603 RC0805 JP20 ERA6Y ERA6YEB323V, RC0805 JP16 ERA6Y ERA6YEB323V, RC0805 JP21 ERA6Y ...
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AD9714/AD9715/AD9716/AD9717 S3 S1 GRN MLX-0532610571 Figure 117. SPI Port Rev Page 07265-189 ...
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C54 100PF C53 100PF 1k RC0603 R24 Figure 118. Modulated Output Rev Page AD9714/AD9715/AD9716/AD9717 C73 100PF ETC1-1-13 1k RC0603 R61 07265-190 ...
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AD9714/AD9715/AD9716/AD9717 CC0402 RC0805 CC0402 HSMS-281C Figure 119. Clock Driver Chip Rev Page 07265-191 ...
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SILKSCREENS AD9714/AD9715/AD9716/AD9717 Figure 120. Layer 2, Ground Plane Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 121. Layer 3, Power Plane Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 122. Assembly—Primary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 123. Assembly—Secondary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 124. Solder Mask—Primary Side with Socket Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 125. Solder Mask—Secondary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 126. Hard Gold Plated with Bumps and Socket Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 127. Primary Side Paste Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 128. Secondary Side Paste Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 129. Silkscreen—Primary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 130. Silkscreen—Secondary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 131. Layer 1—Primary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 132. Layer 4—Secondary Side Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 133. Immersion Gold, No Socket, No Bumps Rev Page ...
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AD9714/AD9715/AD9716/AD9717 Figure 134. Solder Mask—Primary Side, No Socket Rev Page ...
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AD9714/AD9715/AD9716/AD9717 BILL OF MATERIALS Table 18. Qty Reference Designator Device 6 C1, C2, C4, C5, C32, C57 CAPSMDA 17 C3, C6, C7, C8, C9, C10, C11, CC0603 C15, C16, C22, C24, C26, C27, C48, C60, C61, C107 11 C12, C14, ...
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Qty Reference Designator Device 11 L1, L2, L3, L4, L5, L6, L7, IND1812 L12, L13, L16, L19 4 L8, L9, L10, L11 IND1008 4 L14, L17, L18, L20 IND1008 1 L15 IND1210 1 P1 USB-MINIB 1 P3 Molex 0532610571 2 ...
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AD9714/AD9715/AD9716/AD9717 Qty Reference Designator Device 2 RP3, RP4 RNETCTS743-8 2 SW1, SW2 KEYBDSWG 4 T1, T2, T3, T6 ADTL1- ETC1-1-13 2 T5, T8 ADT9- JTX-4-10T 16 LOOPMINI TP1, TP3, TP17, TP18, TP19, TP20, TP22, TP25, TP26, ...
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... AD9715BCPZRL7 −40°C to +85°C AD9716BCPZ 1 −40°C to +85°C 1 AD9716BCPZRL7 −40°C to +85°C 1 AD9717BCPZ −40°C to +85°C 1 AD9717BCPZRL7 −40°C to +85°C 1 AD9714-EBZ 1 AD9715-EBZ 1 AD9716-EBZ 1 AD9717-EBZ RoHS Compliant Part. 6.00 BSC SQ 0.60 MAX 0.50 ...
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AD9714/AD9715/AD9716/AD9717 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07265-0-3/09(A) Rev Page ...