MAX510ACWE+ Maxim Integrated Products, MAX510ACWE+ Datasheet - Page 11

• Manufacturer Part Number: MAX510ACWE+
• Description: IC DAC 8BIT QUAD R-R 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX510ACWE+

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 762mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 12-bit serial input format shown in Figure 3 com-
prises two DAC address bits (A1, A0), two control bits
(C1, C0) and eight bits of data (D0...D7).
The 4-bit address/control code configures the DAC as
shown in Table 1.
When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.
This command directly loads the selected DAC register
at CS's rising edge. A1 and A0 set the DAC address.
Current shift-register data is placed in the selected
input and DAC registers.
For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 1V, DAC B = 2V, DAC
C = 3V and DAC D = 4V), five commands are required.
First, perform four single input register update opera-
tions. Next, perform an “LDAC” command as a fifth
command. All DACs will be updated from their respec-
tive input registers at the rising edge of CS.
Figure 3. Serial Input Format
(LDAC = H)
(LDAC = H)
Address
Address
A1
A1
DOUT
Load Input Register, DAC Registers Unchanged
A0
A0
Serial Input Data Format and Control Codes
A1 A0 C1 C0 D7 D6
C1
C1
This is the first bit shifted in
0
1
Control and
Address bits
C0
C0
1
1
______________________________________________________________________________________
D7
D7
Load Input and DAC Registers
D6
D6
MSB
(Single Update Operation)
D5
D5
8-bit DAC data
8-Bit Data
8-Bit Data
D4
D4
● ● ●
D3
D3
D1 D0
D2
D2
LSB
D1
D1
DIN
D0
D0
with Rail-to-Rail Outputs
Quad, Serial 8-Bit DACs
All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLR if code 00 hex is pro-
grammed, which clears all DACs.
The NOP command (no operation) allows data to be shift-
ed through the MAX509/MAX510 shift register without
affecting the input or DAC registers. This is useful in daisy
chaining (also see the Daisy-Chaining Devices section).
For this command, the data bits are "Don't Cares." As an
example, three MAX509/MAX510s are daisy-chained (A, B
and C), and DAC A and DAC C need to be updated. The
36-bit-wide command would consist of one 12-bit word for
device C, followed by an NOP instruction for device B and
a third 12-bit word with data for device A. At CS's rising
edge, only device B is not updated.
All DAC registers are updated with the contents of their
respective input registers at CS's rising edge. With the
exception of using CS to execute, this performs the
same function as the asynchronous LDAC.
Mode 1 resets the serial output DOUT to transition at
SCLK's rising edge. This is the MAX509/MAX510’s
default setting after the supply voltage has been
applied.
The command also loads all DAC registers with the con-
tents of their respective input registers, and is identical to
the “LDAC” command.
(LDAC = x)
(LDAC = x)
(LDAC = x)
(LDAC = x)
A1
A1
A1
x
0
A1
1
x
Set DOUT Phase – SCLK Rising (Mode 1, Default)
A0
A0
A0
A0
1
x
0
1
C1
C1
C1
C1
0
1
0
1
C0
C0
C0
C0
0
0
Update All DACs from Shift Registers
0
0
D7
D7
D7
D7
x
x
x
“LDAC” Command (Software)
D6
D6
D6
D6
x
x
x
D5
D5
D5
D5
x
x
x
8-Bit DAC Data
D4
D4
D4
D4
No Operation (NOP)
x
x
x
D3
D3
D3
D3
x
x
x
D2
D2
D2
D2
x
x
x
D1
D1
D1
D1
x
x
x
D0
D0
D0
D0
x
x
11
x