LTC1257CS8 Linear Technology, LTC1257CS8 Datasheet - Page 6

• Manufacturer Part Number: LTC1257CS8
• Description: IC D/A CONV 12BIT VOLT OUT 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1257CS8

• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.75mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LSB: The least significant bit or the ideal voltage difference
between two successive codes.
Resolution: The resolution is the number of DAC output
states (2
does not imply linearity.
INL: End-point integral nonlinearity is the maximum de-
viation from a straight line passing through the end-points
of the DAC transfer curve. Because the part operates from
a single supply and the output cannot go below ground,
the linearity is measured between full-scale and the first
code that guarantees a positive output. The INL error at a
given input code is calculated as follows:
DNL: Differential nonlinearity is the difference between
the measured change and the ideal 1LSB change between
any two adjacent codes. The DNL error between any two
codes is calculated as follows:
LTC1257
DEFI ITIO S
6
LSB = (V
n
V
V
INL
V
V
DNL
OS
FS
IDEAL
OUT
V
OUT
U
= The number of digital input bits
= The zero code error or offset of the DAC
= The full-scale output voltage of the DAC
n
= (V
= (Code)(LSB) + V
= The output voltage of the DAC measured at
measured when all bits are set to 1
) that divide the full-scale range. The resolution
= ( V
= The measured voltage difference between
FS
the given input code
two adjacent codes
OUT
– V
U
OUT
OS
– V
)/2
– LSB)/LSB
IDEAL
n
– 1
)/LSB
OS
Offset Error: The theoretical voltage at the output when
the DAC is loaded with all zeros. The output amplifier can
have a true negative offset, but because the part is oper-
ated from a single supply, the output cannot go below
ground. If the offset is negative, the output will remain near
0V resulting in the transfer curve shown in Figure 1.
The offset of the part is measured at the first code that
produces an output voltage 0.5LSB greater than the pre-
vious code:
Full-Scale Error: Full-scale error is the difference be-
tween the ideal and measured DAC output voltages with all
bits set to one (Code = 4095). The full-scale error includes
the offset error and is calculated as follows:
Gain Error: Gain error is the difference between the ideal
and measured slope of the DAC transfer characteristic.
Gain error is equal to full-scale error minus offset error.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
V
FSE
V
V
OS
IDEAL
REF
= V
NEGATIVE
VOLTAGE
OFFSET
OUTPUT
= (V
= (V
= The reference voltage, either internal or
OUT
external
Figure 1. Effect of Negative Offset
– [(Code)(V
{
OUT
REF
)(1 – 2
– V
IDEAL
DAC CODE
–n
FS
) – V
)/LSB
)/(2
OS
n
– 1)]
1257 F01
0V