AD5452YRMZ Analog Devices Inc, AD5452YRMZ Datasheet - Page 21

• Manufacturer Part Number: AD5452YRMZ
• Description: IC DAC 12BIT MULT 50MHZ 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5452YRMZ

• Data Interface: Serial
• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
• Settling Time: 110ns
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resolution (bits): 12bit
• Sampling Rate: 2.7MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 2.5V To 5.5V
• Supply Current: 400nA
• Digital Ic Case: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-BF5xx-to-AD5450/AD5451/AD5452 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin ®
processor and the AD5450/AD5451/AD5452 DAC is shown in
Figure 51. In this configuration, data is transferred through the
MOSI (master output-slave input) pin. SYNC is driven by the SPI
chip select pin, which is a reconfigured programmable flag pin.
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 52. When the SPORT is
enabled, initiate transmission by writing a word to the Tx
register. The data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC’s input shift
register upon the falling edge its SCLK. The DAC output is
updated by using the transmit frame synchronization (TFS) line
to provide a SYNC signal.
80C51/80L51-to-AD5450/AD5451/AD5452 Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 53. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, while RxD drives the serial data line,
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-BF5xx*
ADSP-BF5xx*
Figure 52. ADSP-BF5xx SPORT-to-AD5450/AD5451/AD5452 Interface
Figure 51. ADSP-BF5xx-to-AD5450/AD5451/AD5452 Interface
SPIxSEL
Setting
1
1
00
1
1
1
1111
SCLK
MOSI
SCK
TFS
DT
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
SYNC
SDIN
SCLK
AD5450/AD5451/
SYNC
SDIN
SCLK
AD5450/AD5451/
AD5452*
AD5452*
Rev. 0 | Page 21 of 28
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
to drive SYNC . As data is transmitted to the switch, P1.1 is taken
low. The 80C51/80L51 transmit data only in 8-bit bytes; there-
fore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller on the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between
the DAC and microcontroller interface. P1.1 is taken high
following the completion of this cycle. The 80C51/80L51
provide the LSB of its SBUF register as the first bit in the data
stream. The DAC input register acquires its data with the MSB
as the first bit received. The transmit routine should take this
into account.
MC68HC11-to-AD5450/AD5451/AD5452 Interface
Figure 54 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the AD5516.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5516, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid upon the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To load data to
the DAC, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
MC68HC11*
8051*
Figure 53. 80C51/80L51-to-AD5450/AD5451/AD5452 Interface
Figure 54. MC68HC11-to-AD5450/AD5451/AD5452 Interface
MOSI
P1.1
RxD
SCK
TxD
PC7
AD5450/AD5451/AD5452
SCLK
SDIN
SYNC
SYNC
SCLK
SDIN
AD5450/AD5451/
AD5450/AD5451/
AD5452*
AD5452*