AD9706BCPZ Analog Devices Inc, AD9706BCPZ Datasheet - Page 31

• Manufacturer Part Number: AD9706BCPZ
• Description: IC DAC TX 12BIT 175MSPS 32-LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9706BCPZ

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 50mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Inl ±: 1.48LSB
• Update Rate: 175MSPS
• Output Type: Current
• Termination Type: SMD
• Supply Voltage Max: 3.6V
• No. Of Bits: 12 Bit
• Leaded Process Compatible: Yes
• Dnl±: 1.17LSB
• No. Of Dacs: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9706-EBZ - BOARD EVAL FOR AD9706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SPI REGISTER MAP
Table 15.
Mnemonic
SPI CTL
DATA
VERSION
CALMEM
MEMRDWR
MEMADDR
MEMDATA
TRIM
SCLK
SDIO
SCLK
CSB
SDO
SDIO
SCLK
SDIO
CSB
CSB
Figure 72. Serial Register Interface Timing, MSB First Write
Figure 73. Serial Register Interface Timing, MSB First Read
Figure 74. Serial Register Interface Timing, LSB First Write
R/W N1 N0 A4 A3
A0
R/W N1 N0 A4 A3
0x00
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x14
Addr
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A1 A2 A3 A4 N0
INSTRUCTION CYCLE
SDIODIR
DATAFMT
CALSTAT
Bit 7
A2 A1 A0
A2 A1 A0 D7
N1 R/W D0
D7
Bit 6
DATADIR
CALEN
0
D6
DATA TRANSFER CYCLE
N
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D1
D6
N
0
D5
N
D2
D5
N
0
N
Bit 5
SWRST
CALMEM[1]
MEMADDR[5]
MEMDATA[5]
D3
D4
D3
0
N
0
D2
D5
D2
0
N
0
D1
D6
D1
0
N
0
D0
D7
D0
0
N
0
Rev. A | Page 31 of 52
DCLKPOL
Bit 4
LNGINS
CALMEM[0]
MEMADDR[4]
MEMDATA[4]
CALDACFS
SCLK
SCLK
SDIO
SCLK
SDIO
SDIO
CSB
SDO
CSB
CSB
Bit 3
PDN
DESKEW
VER[3]
SMEMWR
MEMADDR[3]
MEMDATA[3]
I1
Figure 75. Serial Register Interface Timing, LSB First Read
A0 A1 A2 A3 A4
AD9704/AD9705/AD9706/AD9707
Figure 76. Timing Diagram for SPI Register Write
Figure 77. Timing Diagram for SPI Register Read
I0
INSTRUCTION BIT 7
INSTRUCTION CYCLE
t
t
DS
DS
Bit 2
SLEEP
CLKDIFF
VER[2]
DIVSEL[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
t
PWH
t
DH
t
N0
D7
SCLK
N1 R/W
t
PWL
INSTRUCTION BIT 6
D0
Bit 1
CLKOFF
VER[1]
DIVSEL[1]
MEMADDR[1]
MEMDATA[1]
t
D1
SU
DATA TRANSFER CYCLE
0
D2
D6
0
D4
t
N
HLD
D5
N
Bit 0
EXREF
DIVSEL[0]
CALCLK
VER[0]
UNCAL
MEMADDR[0]
MEMDATA[0]
D6
N
D7
D5
N