AD7805BRSZ Analog Devices Inc, AD7805BRSZ Datasheet - Page 8

• Manufacturer Part Number: AD7805BRSZ
• Description: IC DAC 10BIT QUAD PARALL 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7805BRSZ

• Data Interface: Parallel
• Settling Time: 1.5µs
• Number Of Bits: 10
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 66mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Resolution (bits): 10bit
• Sampling Rate: 667kSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analogue: 3V To 5.5V
• Supply Voltage Range - Digital: 3V To 5.5V
• Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7804/AD7805/AD7808/AD7809
AD7805
Pin No.
1
2, 3
4
5–10,
12, 13
19, 20
11
14
15
16
17
18
21, 22
23
24
25
26, 27
28
AD7809
Pin No.
1, 11, 13,
20, 33
2, 5, 39, 40
41, 42
43
3, 4, 6, 7, 9, DB9–DB2
10, 15, 23
24, 26
8, 12
14
16
17
18
21
19
22, 25
27, 29, 30
31
32
34
35, 36
28, 37, 38
44
AD7805 PIN CONFIGURATION
REFOUT
V
V
AGND
DGND
LDAC
OUT
OUT
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B
A
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Mnemonic
NC
AGND
V
REFOUT
DB1, DB0
V
LDAC
DGND
DV
WR
CS
CLR
V
A2, A1, A0
MODE
REFIN
COMP
V
AV
PD
(Not to Scale)
OUT
OUT
OUT
OUT
TOP VIEW
DD
AD7805
DD
B, V
F, V
H, V
D, V
OUT
OUT
OUT
OUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
E
AD7805/AD7809 PIN FUNCTION DESCRIPTIONS
A
G
C
AV
V
V
COMP
REFIN
MODE
A0
A1
DB0
DB1
CLR
CS
WR
DV
OUT
OUT
DD
DD
Description
No Connect. These pins should be left open circuit.
Ground reference point for analog circuitry.
Analog output voltages from the DACs.
Reference Output. This is a bandgap reference and is typically 1.23 V.
Data Inputs. DB9 to DB2 are the 8 MSBs of the data word.
DB1 and DB0 function as the 2 LSBs of the 10-bit word in 10-bit parallel mode but
have other functions when BYTE loading structure is used.
Analog output voltages from the DACs.
LDAC Input. When this digital input is taken low, all DAC registers are simultaneously
updated with the contents of the DAC data registers. If LDAC is permanently tied low, or is
low during the rising edge of WR similar to data inputs, an automatic update will take place.
Ground reference point for digital circuitry.
Digital Power Supply.
Write Input WR is an active low logic input which is used in conjunction with CS and
the address pins to write data to the relevant registers.
Chip Select. Active low logic input.
Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are
cleared either to V
transfer function of the MAIN DAC will remain centered around the V
Analog output voltages from the DACs.
DAC Address Inputs. These digital inputs are used in conjunction with CS and WR to
determine which DAC channel control register or DAC data register is loaded from the
input register. These address bits are don’t cares when writing to the system control register.
Logic Input. Logic high enables writing to the DAC data registers, a logic low enables
writing to the control registers.
This is an external reference input for the DAC. When this reference is selected for the DAC
in the control register, the analog output from the selected DAC swings around this point.
Compensation Pin. This pin provides an output from the internal V
provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors
to both AV
giving the facility for two external references on the part.
Analog output voltages from the DACs.
Analog Power Supply.
Active low input used to put the part into low power mode reducing current consump-
tion to 1 A.
C
D
DD
and AGND. This pin can be overdriven with an external reference, thus
BIAS
–8–
or to V
BIAS
NC = NO CONNECT
/16 volts. All Sub DACs are also cleared and thus the
AGND
AGND
V
OUT
DB9
DB8
DB7
DB6
DB5
DB4
NC
NC
AD7809 PIN CONFIGURATION
F
10
11
1
2
3
4
5
6
7
8
9
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
PIN 1
IDENTIFIER
(Not to Scale)
TOP VIEW
AD7809
DD
/2 divider and is
BIAS
33
32
31
30
29
28
27
26
25
24
23
point.
NC
REFIN
MODE
A0
A1
AV
A2
DB0
V
DB1
DB2
OUT
DD
G
REV. A