AD9744ARURL7 Analog Devices Inc, AD9744ARURL7 Datasheet - Page 15

• Manufacturer Part Number: AD9744ARURL7
• Description: IC DAC 14BIT 210MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9744ARURL7

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 145mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: AD9744ACP-PCBZ - BOARD EVAL FOR AD9744ACP

The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note that the INL/DNL specifications
for the AD9744 are measured with IOUTA maintained at a
virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the
AD9744.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.2 V for an I
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9744 digital section consists of 14 input bit channels
and a clock input. The 14-bit parallel data inputs follow stan-
dard positive binary coding, where DB13 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold
times can also be varied within the clock cycle as long as the
specified minimum times are met, although the location of
these transition edges may affect digital feedthrough and distortion
performance. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
DIGITAL
OUTA
INPUT
Figure 28. Equivalent Digital Input
and V
OUTFS
= 20 mA to 1 V for an I
OUTB
OUTFS
) due to the nature of a PMOS
. It degrades slightly from its
DVDD
OUTFS
= 2 mA.
Rev. B | Page 15 of 32
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock will
translate directly into the DAC output. Optimal performance
will be achieved if the CLOCK input has a sharp rising edge,
since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in Table 6. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK– input is
left floating. If CMODE is connected to CLKVDD, the differen-
tial receiver mode is selected. In this mode, both inputs are high
impedance. The final mode is selected by floating CMODE.
This mode is also differential, but internal terminations for
positive emitter-coupled logic (PECL) are activated. There is no
significant performance difference among any of the three clock
input modes.
Table 6. Clock Mode Selection
CMODE Pin
CLKCOM
CLKVDD
Float
The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as previously described.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 29. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
Clock Input Mode
Single-Ended
Differential
PECL
AD9744