AD7805BRS Analog Devices Inc, AD7805BRS Datasheet - Page 7

• Manufacturer Part Number: AD7805BRS
• Description: IC DAC 10BIT QUAD PARALL 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7805BRS

• Rohs Status: RoHS non-compliant
• Settling Time: 1.5µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 66mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP

REV. A
AD7804
Pin No.
1
2, 3
4
5
6
7
8
9
10
11
12
13
14, 15
16
AD7808
Pin No.
1, 6
2, 3
4
5
7, 8
9
10
11
12
13
14
15
16
17, 18
20
21
22, 23
19, 24
AD7804 PIN CONFIGURATION
REFOUT
V
V
AGND
DGND
LDAC
OUT
OUT
SDIN
FSIN
B
A
Mnemonic
AGND
V
REFOUT
PD
V
FSIN
LDAC
SDIN
DGND
DV
CLKIN
CLR
NC
V
REFIN
COMP
V
AV
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
DD
DD
(Not to Scale)
TOP VIEW
AD7804
B, V
F, V
H, V
D, V
OUT
OUT
OUT
OUT
E
A
G
C
16
15
14
13
12
11
10
9
AD7804/AD7808 PIN FUNCTION DESCRIPTION
AV
V
V
COMP
REFIN
CLR
CLKIN
DV
OUT
OUT
DD
DD
Description
Ground reference point for analog circuitry.
Analog output voltage from the DACs.
Reference Output. This is a bandgap reference and is typically 1.23 V.
Active low input used to put the part into low power mode reducing current consumption
to 1 A.
Analog output voltages from the DACs.
Level-triggered control input (active low). This is the frame synchronization signal for the
input data. When FSIN goes low, it enables the input shift register and data is transferred
on the falling edges of CLKIN.
LDAC Input. When this digital input is taken low, all DAC registers are simultaneously
updated with the contents of the data registers. If LDAC is tied permanently low, or is
low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic
update will take place.
Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift
register on the falling edge of CLKIN.
Ground reference point for digital circuitry.
Digital Power Supply.
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.
Duty Cycle should be between 40% and 60%.
Asynchronous CLR Input. When this input is taken low, all Main DAC outputs are
cleared either to V
transfer function of the Main DAC will remain centered around the V
No Connect. This pin should be left open circuit.
Analog output voltages from the DACs.
This is an external reference input for the DACs. When this reference is selected for a
DAC in the control register, the analog output from the selected DAC swings around this
point.
Compensation Pin. This pin provides an output from the internal V
provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors
to both AV
giving the facility for two external references on the part.
Analog output voltage from the DACs.
Analog Power Supply. +3.3 V to +5 V.
C
D
DD
and AGND. This pin can be overdriven with an external reference, thus
BIAS
–7–
or to V
BIAS
AD7804/AD7805/AD7808/AD7809
/16 volts. All Sub DACs are also cleared and thus the
AD7808 PIN CONFIGURATION
REFOUT
V
V
V
V
AGND
DGND
AGND
LDAC
OUT
OUT
OUT
OUT
SDIN
FSIN
PD
B
A
F
E
12
10
11
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD7808
24
23
22
21
20
19
18
17
16
15
14
13
DV
AV
V
V
COMP
REFIN
AV
V
V
NC
CLR
CLKIN
DD
OUT
OUT
OUT
OUT
DD
DD
DD
BIAS
/2 divider and is
C
D
G
H
point.