SSDUSMS0004G1 Intel, SSDUSMS0004G1 Datasheet - Page 17

• Manufacturer Part Number: SSDUSMS0004G1
• Manufacturer: Intel
• Type: Solid State Driver

Specifications of SSDUSMS0004G1

• Density: 4GByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: BGA
• Mounting: Surface Mount
• Pin Count: 168
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / Rohs Status: Compliant

Intel® Z-P140 PATA SSD
Table 13.
6.2
6.2.1
Table 14.
October 2008
Order Number: 318890-003US
ALE-0, ALE-1
ALE-2, ALE-3
CE0#-0, CE1#-0
CE0#-1, CE1#-1
CE0#-2, CE1#-2
CE0#-3, CE1#-3
CLE-0, CLE-1
CLE-2, CLE-3
RE#-0, RE#-1
RE#-2, RE#-3
WE#-0, WE#-1
WE#-2, WE#-3
WP#-0, WP#-1
WP#-2, WP#-3
DQ[00...07]-0
DQ[00...07]-1
DQ[00...07]-2
DQ[00...07]-3
Signal Name
RESET#
RE#-0
RE#-1
RE#-2
RE#-3
VDDC
VCC
RFU
Symbol
Signal Locator (Continued)
Signal Descriptions
BGA NAND Signals
BGA NAND Signal Descriptions
M1, M17, P1,
Location
E17, F17
BGA
A11
U11
B11
G15
T11
P17
D3
Input / Output
Type
Input
Input
Input
Input
Input
Input
Signal Name
Address latch enable (channels 0, 1, 2 and 3): During the time ALE is HIGH,
address information is transferred from I/O[7:0] into the on-chip address
register on the rising edge of WE#. When address information is not being
loaded, ALE should be driven LOW.
Chip enable (Channels 0, 1, 2 and 3): Gates transfers between the host
system and the NAND Flash device. After the device starts a PROGRAM or
ERASE operation, CE# can be de-asserted. For the 8 Gb configuration, CE0#
controls the first 4 Gb of memory; CE1# controls the second 4 Gb of memory.
For the 16 Gb configuration, CE0# controls the first 8 Gb of memory; CE1#
controls the second 8 Gb. See the Bus Operation section, starting on
for additional operational details.
Command latch enable (channels 0, 1, 2 and 3): When CLE is HIGH,
information is transferred from I/O[7:0] to the on-chip command register on
the rising edge of WE#. When command information is not being loaded, CLE
should be driven LOW.
Read enable: Gates transfers from the NAND Flash device to the host system.
Write enable: Gates transfers from the host system to the NAND Flash device.
Write protect: Protects against inadvertent PROGRAM and ERASE operations.
All PROGRAM and ERASE operations are disabled when WP# is LOW.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and
instruction information between the PoP PATA controller and the additional
BGA NAND devices. Data is output only during READ operations; at other
times the I/Os are inputs.
VDDC_0
VDDF_0
WE#-0
WE#-1
WE#-2
WE#-3
VDDF
VSS
C1, C8, C10,
C17, R1, R8,
Location
R10, R17
H17, J17
E1, F1
H1, J1
BGA
A6
U6
B6
T6
Description
XTALIN / XTALI
Signal Name
XTALC / IO3
XTALSEL
XTALR /
WP#-0
WP#-1
WP#-2
WP#-3
Intel® Z-P140 PATA SSD
Product Manual
Location
BGA
page
C5
R5
C4
R4
E3
E2
F2
15,
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