SI-7600 Allegro Microsystems Inc, SI-7600 Datasheet - Page 4

• Manufacturer Part Number: SI-7600
• Manufacturer: Allegro Microsystems Inc

Specifications of SI-7600

• Lead Free Status / Rohs Status: Not Compliant

3-Phase Stepper Motor Driver ICs (Star Connection/Delta Connection)
6. Method of Calculating Power Loss of Output
The SI-7600 uses a MOS-FET array for output. The power loss
of this MOS FET array can be calculated as summarized below.
This is an approximate value that does not reflect parameter
variations or other factors during use in the actual application.
Therefore, heat from the MOS FET array should actually be
measured.
To calculate the power loss of the MOS FET array, the following
parameters are needed:
(1) Control current Io (max)
(2) Excitation method
(3) Chopping ON-OFF time at current control: T
(4) ON resistance of MOS FET: R
(5) Forward voltage of MOS FET body diode: V
For (4) and (5), use the maximum values of the MOS FET speci-
fications.
(3) should be confirmed on the actual application.
The power loss of Pch MOS FETs is caused by the ON resis-
tance and by the chopping-OFF regenerative current flowing
through the body diodes in Fast Decay mode.
(In Slow Decay mode, the chopping-OFF regenerative current
does not flow the body diodes.)
The losses are
With these parameters, the loss Pp per MOS FET is calculated
depending on the actual excitation method as follows:
a) 2-phase excitation (T=T
b) 2-3 phase excitation (T=T
Relationship between RC terminal voltage and output current
ITrip
1.5V
0.5V
Parameters for calculating power loss
Power loss of Pch MOS FETs
ON resistance loss P1: P1=I
Body diode loss P2: P2=I
MOS FET
P
P
(T
I
V
P
P
OUT
= (P1 T
= (P1 T
RC
ON
: ON time, T
T) (1/12)
ON
ON
/T+P2 t
/T+P2 t
OFF
Ton
: OFF time, t
Fast
Decay
OFFf
OFFf
/T) (1/3)
ON
/T) (1/4)+(0.5 P1 T
M
ON
+T
V
M
+T
SD
2
OFF
Slow Decay
DS (ON)
R
OFF
OFFf
Toff
)
DS (ON)
)
: Fast Decay time at OFF)
ON
SD
ON
, T
/T+P2 t
OFF
, t
OFFf
V
OFFf
PFD
/
The power loss of Nch MOS FETs is caused by the ON resis-
tance or by the chopping-OFF regenerative current flowing
through the body diodes.
(This loss is not related to the current control method, Slow,
Mixed, or Fast Decay.)
The losses are
ON resistance loss N1: N1=I
Body diode loss N2: N2=I
With these parameters, the loss P
depending on the actual excitation method as follows:
a) 2-phase excitation (T=T
b) 2-3 phase excitation (T=T
If the SLA5017 is used in an output section, the power losses of
a Pch MOS FET and an Nch MOS FET should be multiplied by
three and added to determine the total loss P of SLA5017.
In other words, P=3 P
The allowable losses of SLA5017 are
Select a heatsink by considering the calculated losses, allow-
able losses, and following ratings:
When selecting a heatsink for SLA5017, be sure to check the
product temperature when in use in an actual applicaiton.
The calculated loss is an approximate value and therefore con-
tains a degree of error.
Select a heatsink so that the surface Al fin temperature of
SLA5017 will not exceed 100 C under the worst conditions.
Determining power loss and heatsink when SLA5017 is
Power loss of Nch MOS FETs
used
Without heatsink: 5W j-a=25 C/W
Infinite heatsink: 35W j-c=3.57 C/W
P
P
N
N
=(N1+N2 T
=(N1+N2 T
(W)
15
10
5
0
0
OFF
OFF
25
Ambient temperature Ta ( C)
/T) (1/3)
/T) (1/4)+(0.5N1+N2 T
P
+3 P
M
50
ON
V
M
+T
ON
N
SD
2
+T
OFF
R
75
DS(ON)
OFF
N
)
per MOS FET is calculated
)
100
SI-7600/SI-7600D
OFF
125
/T) (1/12)
SI-7600/SI-7600D
150
101