CP3SP33SMRNOPB National Semiconductor, CP3SP33SMRNOPB Datasheet
CP3SP33SMRNOPB
Specifications of CP3SP33SMRNOPB
Related parts for CP3SP33SMRNOPB
CP3SP33SMRNOPB Summary of contents
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... Microwire/ GPIO Wake-Up SPI 0 Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor. Teak is a registered trademark of ParthusCeva, Inc. TRI-STATE is a registered trademark of National Semiconductor Corporation. ©2007 National Semiconductor Corporation ©2007 Mentor Graphics Corporation In addition to providing the features needed for the next gen- ...
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General Description . . . . . . . . . . . . . . . . . . . . . . 1 2.0 Features . . . . . . . . . . . . ...
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Features CPU Features ! Fully static RISC processor core, capable of operating from MHz with zero wait/hold state ! Minimum 10.4 ns instruction cycle time with a 96-MHz in- ternal clock frequency, based on a 12-MHz ...
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Device Overview The CP3SP33 connectivity processor is an advanced mi- crocomputer with system timing, interrupt logic, instruction cache, data memory, and I/O ports included on-chip, mak- ing it well-suited to a wide range of embedded applications. The block diagram ...
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CAN INTERFACE The two CAN modules support Full CAN 2.0B class, CAN serial bus interfaces for applications that require a high- speed ( Mbits per second low-speed interface with CAN bus master capability. The data ...
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MICROWIRE/SPI The two Microwire/SPI (MWSPI) interface modules support synchronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. The maximum bus clock frequency is 12 MHz. ...
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... CP3SP33 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth Development Board, Bluetooth Protocol Stack, and Applica- tion Software. See your National Semiconductor sales rep- resentative for current information on availability and features of emulation equipment and evaluation boards. 7 with National’ ...
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Signal Descriptions Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific pe- ripherals or interfaces. These pins may be individually con- figured as port pins, even when the associated peripheral or interface ...
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Name Pins I/O Input 12 MHz Clock Input CLKIN 1 Input 12 MHz Oscillator Input X1CKI 1 Output 12 MHz Oscillator Output X1CKO 1 Input 32 kHz Oscillator Input X2CKI 1 Output 32 kHz Oscillator Output X2CKO 1 Input Chip ...
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Name Pins I/O CPU JTAG Test Mode Select Input TMS 1 (with internal weak pullup) CPU JTAG Test Clock Input TCK 1 Input (with internal weak pullup) CPU JTAG Test Data Input Input TDI 1 (with internal weak pullup) TDO ...
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Name Pins I/O Primary Function Codec ADC1 External Filter 1 Input TCVBUF1 Capacitor Pin (1.5V) Codec ADC2 External Filter TCVBUF2 1 Input Capacitor Pin (1.5V) Codec ADC1 External Filter 1 Input TCVCM1 Capacitor Pin (0.9V) Codec ADC2 External Filter 1 ...
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Name Pins I/O 1 I/O Generic I/O PE0 1 I/O Generic I/O PE1 1 I/O Generic I/O PE2 1 I/O Generic I/O PE3 1/0 I/O Generic I/O PE4 1 I/O Generic I/O PE5 1 I/O Generic I/O PE6 1 I/O ...
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Name Pins I/O Primary Function 1 I/O Generic I/O PF0 1 I/O Generic I/O PF1 1 I/O Generic I/O PF2 1 I/O Generic I/O PF3 1 I/O Generic I/O PF4 1/0 I/O Generic I/O PF5 1/0 I/O Generic I/O PF6 ...
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Name Pins I/O 1 I/O Generic I/O PG0 1 I/O Generic I/O PG1 1 I/O Generic I/O PG2 1 I/O Generic I/O PG3 1/0 I/O Generic I/O PG4 1/0 I/O Generic I/O PG5 1/0 I/O Generic I/O PG6 1/0 I/O ...
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Name Pins I/O Primary Function 1/0 I/O Generic I/O PH0 1 I/O Generic I/O PH1 1 I/O Generic I/O PH2 1 I/O Generic I/O PH3 1/0 I/O Generic I/O PH4 1/0 I/O Generic I/O PH5 1/0 I/O Generic I/O PH6 ...
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CPU Architecture The CP3SP33 uses the CR16CPlus third-generation 16-bit CompactRISC processor core. The CPU implements a Re- duced Instruction Set Computer (RISC) architecture that al- lows an effective execution rate one instruction per clock cycle. For ...
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Interrupt Base Register (INTBASE) The INTBASE register holds the address of the dispatch ta- ble for exceptions. The dispatch table can be located any- where in the CPU address space. When loading the INTBASE register, bits ...
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CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various oper- ating modes and to control optional on-chip caches. All CFG bits are cleared on reset Reserved ...
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ADDRESSING MODES The CR16CPlus CPU core implements a load/store archi- tecture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessi- ble in registers using load and store instructions. For effi- cient implementation of ...
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STACKS A stack is a last-in, first-out data structure for dynamic stor- age of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. ...
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Mnemonic Operands MOVi Rsrc/imm, Rdest MOVXB Rsrc, Rdest MOVZB Rsrc, Rdest MOVXW Rsrc, RPdest MOVZW Rsrc, RPdest MOVD imm, RPdest RPsrc, RPdest ADD[U]i Rsrc/imm, Rdest ADDCi Rsrc/imm, Rdest ADDD RPsrc/imm, RPdest MACQWa Rsrc1, Rsrc2, RPdest MACSWa Rsrc1, Rsrc2, RPdest MACUWa ...
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Mnemonic ASHUD Rsrc/imm, RPdest LSHi Rsrc/imm, Rdest LSHD Rsrc/imm, RPdest SBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT Rposition/imm, Rsrc TBITi Iposition, disp(Rbase) Iposition, disp(RPbase) ...
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Mnemonic Operands RETX PUSH imm, Rsrc, RA POP imm, Rdest, RA POPRET imm, Rdest, RA LOADi disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest LOADD disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest STORi Rsrc, disp(Rbase) ...
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Mnemonic STORMP imm3 DI EI EIWAIT NOP WAIT CINV [i] www.national.com Table 3 Instruction Set Summary Operands Store registers (R2-R5, R8-R11) to memory starting at (R7,R6) Disable maskable interrupts Enable maskable interrupts Enable maskable interrupts and wait ...
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Memory The CP3SP33 supports a uniform 256M-byte linear ad- dress space. Program memory must reside in the first 16M bytes of the address space. Table 4 lists the types of mem- Start End Address Address 0000 0000h 0000 7FFFh ...
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Start End Address Address 00FF 9800h 00FF 9BFFh 00FF 9C00h 00FF 9FFFh 00FF A000h 00FF A3FFh 00FF A400h 00FF A7FFh 00FF A800h 00FF ABFFh 00FF AC00h 00FF AFFFh 00FF B000h 00FF B7FFh 00FF B800h 00FF BBFFh 00FF BC00h 00FF BFFFh ...
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Instruction Cache The CPU instruction cache has the following features bytes data memory ! 4-way set-associative organization ! Critical word first, with wrapping cache entry fill ! Pseudo Least Recently Used (PLRU) allocation policy ! Cache locking ...
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CACHE INVALIDATION The cache does not snoop any bus cycles. Software is re- sponsible for invalidating the cache when the CPU or any other device writes to program memory. The cache is invalidated by executing the CINV [i] instruc- ...
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CPU Core Bus Arbitration The CPU core AHB bus can be controlled by either of two bus masters: ! CPU Core ! CPU DMA Controller The bus arbiter implements two levels of priority arbitration among the potential bus masters: ...
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Default Master Register (DFTMAST) The DFTMAST register is a 32-bit, read/write register that selects the master number of the default bus master. After reset, this register is initialized to 0000 0002h Reserved DFTMAST The Default Master ...
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... DSP and Audio Peripherals The CP3SP33 includes a Teak DSP for supporting high-per- formance audio applications. DSP software packages are available from National Semiconductor for signal process- ing operations commonly used to process audio data. The DSP implements 16-bit fixed-point arithmetic with a 4- bus ( and Program) Harvard architecture ...
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DSP MEMORY SPACES The DSP has a four-bus architecture. Instructions are re- ceived on the 16-bit P bus, the DSP data memory is access- ed through the 16-bit X and Y buses, and external memory and DSP peripherals are ...
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Downloading to DSP Program Memory The CPU interface can be used to download software to the DSP memories. After power-on-reset or other system re- sets, the DSP will be held in reset with the DSP clock (Aux- iliary Clock ...
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The ASC multiplexes interrupt request signals from devices capable of requesting interrupts from either of the CPU and DSP interrupt controllers. These requests are assigned to ASC interrupt channels 0 to 10, as shown in Table 12. Table 11 ASC ...
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DSP AND ASC REGISTERS The DSP and ASC registers control and provide status for the interface between the CPU and the DSP. The DSP and ASC registers are listed in Table 13. Table 13 DSP and ASC Registers Name ...
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DSP DMA Channel 0 Data Register (PDATA) The PDATA register is a 16-bit, read/write register that pro- vides the CPU with access to the read and write FIFOs for DSP DMA channel 0. Writing the register loads the write ...
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CPU/DSP Interface Status Register (PSTS) The PSTS register is a 16-bit, read-only register that pro- vides status bits for the CPU/DSP interface WFFI RFNEI RFFI Reserved RCOMIM2 RCOMIM1 RCOMIM0 RRI2 ...
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CPU-to-DSP Semaphore Clear Register (PCLEAR) The PCLEAR register is a 16-bit, write-only register used by the CPU to clear interrupt requests from the DSP. Writing 1 to bits in the PCLEAR register clears the corresponding bits in the APBP_SEM ...
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ASC Interrupt Select Register (ASCINTSEL) The ASCINTSEL register is a 16-bit, read/write register that selects between the CPU and DSP interrupt controllers for the ASC interrupt channels (listed in Table 11). Clear bits select the CPU interrupt controller, and ...
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External Bus Interface Unit The External Bus Interface Unit (EBIU) provides a memory bus interface that supports three types of external memory: ! Asynchronous RAM ! Page-Mode Flash Memory ! ROM Because the CP3SP33 does not have on-chip non-volatile ...
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EXTERNAL BUS CYCLE TIMING Figure 6 shows the timing of a read cycle on the external memory bus. Figure 6. Read Cycle Timing Figure 7 shows the timing of a write cycle on the external memory bus. Figure 7. ...
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EBIU REGISTERS For all registers, the contents should only be changed once, in the initialization routine after reset. The EBIU has two global control registers, two registers specific to each chip select, and 3 registers for defining 3 sets ...
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Mask Register n (SMSKRn) The SMSKRn registers are 32-bit, read/write registers that specify timing parameters, memory type, and memory size for the chip selects. At reset, the SMSKR0 register is initial- ized to 0000 0028h, SMSKR1 is initialized to ...
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Flash t Timing Register (FLASH_TRPDR) RPD The FLASH_TRPDR register is a 32-bit, read/write register that specifies the number of clock cycles between flash memory reset/power-down and the first flash read/write cy- cle. At reset, the FLASH_TRPDR register is initialized ...
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System Configuration 11.1 OPERATING ENVIRONMENT The operating environment controls the reset vector (boot address). In ERE16 mode, the vector is 0040 0000h. In ERE32 mode, the vector is 0080 0000h. The operating mode of the device is controlled by ...
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ENV1SEL The ENV1 Select bit selects an internal clock signal to be available for driving on the ENV1 pin. The ENV1OE bit must be set to enable driving the selected signal on the ENV1 pin. – 0 Main Clock is ...
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CPU DMA Controller The CPU DMA controller (DMAC) can be used to accelerate peripheral-to-memory, memory-to-peripheral, and memory- to-memory block transfers. Because it uses cycle stealing to interleave bus cycles with the CPU, DMA-based data move- ment uses the available ...
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Trans- SRCRQ Peripheral action 27 CVSD/PCM0 R 28 CVSD/PCM0 W 29 CVSD/PCM1 R 30 CVSD/PCM1 W 31 AAI Slot AAI Slot MWSPI0 R 34 MWSPI0 W 35 ACCESS.bus 0 R/W The DMA request and ...
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When the PF bit in the DMACNTn register is clear, the DMAC is the flow controller for the transfer. When the PF bit is set, the peripheral is ...
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Termination The DMA transfer is terminated when the DMACNTn.CHEN bit is cleared. 12.4 SOFTWARE DMA REQUEST In addition to the hardware requests from peripherals, a DMA transfer request can also be initiated by software. A software DMA transfer request is ...
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Table 23 DMA Controller Registers Name Address Request Timeout RQTR1 FF 0458h Request Timeout RQTCNT1 FF 045Ch Counter Register DMACNT1 FF 0460h DMA Control Register DMASTAT1 FF 0464h DMA Status Register Device A Address ADCA2 FF 0480h Counter Register Device ...
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Table 23 DMA Controller Registers Name Address RQTR6 FF 0598h RQTCNT6 FF 059Ch DMACNT6 FF 05A0h DMASTAT6 FF 05A4h ADCA7 FF 05C0h ADRA7 FF 05C4h ADCB7 FF 05C8h ADRB7 FF 05CCh BLTC7 FF 05D0h BLTR7 FF 05D4h RQTR7 FF 05D8h ...
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Table 23 DMA Controller Registers Name Address Request Timeout RQTR11 FF 06D8h Request Timeout RQTCNT11 FF 06DCh Counter Register DMACNT11 FF 06E0h DMA Control Register DMASTAT11 FF 06E4h DMA Status Register Device A Address ADCA12 FF 0700h Counter Register Device ...
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Device A Address Register n (ADRAn) The Device A Address register is a 32-bit, read/write regis- ter. It holds the starting address of either the next source data block, or the next destination data area, according to the DIR ...
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EOVR If the Enable Interrupt on OVR bit is set, it en- ables an interrupt when the DMASTAT.OVR bit is set. – 0 Interrupt disabled. – 1 Interrupt enabled. ETO If the Enable Interrupt on Timeout bit is set, it ...
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DMA Status Register n (DMASTATn) The DMA status register is a 32-bit register that holds the status information for the DMA channel. This register is cleared at reset. The reserved bits always return zero when read. The ERR, VLD, ...
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Interrupts The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. The highest-priority interrupt is the Non- Maskable Interrupt (NMI), which is triggered by a falling edge received on the ...
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IRQn Description IRQ38 USART0 CTS IRQ37 TA0 (MFT0 Port A) IRQ36 TB0 (MFT0 Port B) IRQ35 TA1 (MFT1 Port A) IRQ34 TB1 (MFT1 Port B) IRQ33 VTU0A (VTU Interrupt Request 1) IRQ32 VTU0B (VTU Interrupt Request 2) IRQ31 VTU0C (VTU ...
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If the six IRQ1 through IRQ6 interrupts are asserted, then IRQ6 is taken because this interrupt belongs to the highest priority group (lowest group number), and it has the highest channel number within that group. If only IRQ1 and IRQ5 ...
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Interrupt Vector Register (IVCT) The IVCT register is a 32-bit, read-only register which re- ports the encoded value of the highest priority maskable in- terrupt that is both asserted and enabled. The register is read by the CPU during ...
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Interrupt Enable and Mask Register 0 (IENR0) The IENR0 register is a 32-bit, read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ1 to IRQ31. The register is initialized to 0000 0000h at reset. ...
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Software Interrupt Register 0 (SOFTR0) The SOFTR0 register is a 32-bit, read/write register. Setting a bit in this register activates the corresponding maskable interrupt IRQ31 to IRQ1. Bit 0 of this register is reserved. The register is initialized to ...
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Interrupt Priority Group B Register 0 (INTGPBR0) The INTGPBR0 register is a 32-bit, read/write register. Bits in this register specify the most significant bit for selecting the priority group of the corresponding interrupt IRQ31 to IRQ1. Bit 0 of ...
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Clock Generation The clock circuitry includes oscillators for generating a 12- MHz Main Clock and an optional 32.768-kHz Slow Clock from external crystal networks. Alternatively, either clock may be replaced by an external clock source. Two identical PLLs are ...
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EXTERNAL CRYSTAL NETWORKS An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock, unless an external clock signal is driven on the CLKIN pin. A similar external crystal network may be used ...
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SLOW CLOCK Slow Clock is necessary for operating the device in reduced power modes and to provide a clock source for modules such as the Timing and Watchdog Module. The low-frequency oscillator may be used to generate Slow Clock ...
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F must be between 2 and 4 MHz. F REF 153 MHz. The output frequency F is derived from the input fre- OUT quency described by the following equation: IN NDIV + -------------------------------------- ...
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HCLK CLOCK HCLK Clock drives the CPU and the modules on the CPU core AHB bus generated by a 12-bit prescaler from Main Clock, PLL1 Clock, or PLL2 Clock. The prescaler al- lows setting the HCLK Clock ...
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Figure 16 is block diagram of the auxiliary clock generation logic. Figure 16. Auxiliary Clock Generators 69 www.national.com ...
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CLOCK GENERATION REGISTERS Table 32 lists the clock generation registers. Table 32 Clock and Reset Registers Name Address PMMCKCTL FF A400h PMMSR FF A408h PMMPRSHC FF A40Ch PMMPRSPC FF A410h PMMPRSSC FF A414h PMMPLL1CTL1 FF A420h PMMPLL1CTL2 FF A424h ...
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Clock and Reset Control Register (PMMCKCTL) The PMMCKCTL register is a byte-wide, read/write register that controls the clock selection and contains the power-on reset status bit. At reset, the PMMCKCTL register is initial- ized as described below ...
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Slow Clock Prescaler Register (PMMPRSSC) The PMMPRSSC register is a 16-bit, read/write register that holds the 14-bit prescaler available to generate Slow Clock from Main Clock. The register is initialized to 02DBh at re- set Reserved ...
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PLLn N Mod Register (PMMPLLnNMOD) The PMMPLLnNMOD registers are 16-bit, read/write regis- ters that hold the 5-bit fractional part of the N divisor for the corresponding PLL and a control field for the level of dither- ing in effect. ...
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Reset There are five sources of reset: ! Power-On Reset —on-chip power-on detector and timer. ! External Reset —assertion of the RESET input. ! Software Reset —enabled by writing special code se- quences to the SWRESET register. ! Timing ...
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Manual and SDI External Reset An external reset circuit based on the LM3724 5-Pin Micro- processor Reset Circuit is shown in Figure 19. The LM3724 produces a 190-ms logic low reset pulse when the power supply rises above a ...
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Power Management Module The Power Management Module (PMM) improves the effi- ciency of the CP3SP33 by changing the operating mode (and therefore the power consumption) according to the re- quired level of device activity. The device implements four power ...
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ACTIVE MODE In Active mode, the high-frequency oscillator is active and generates the 12-MHz Main Clock. If the PLL Clocks are not needed, the PLLs may remain powered off. Most devices on the CPU core bus are driven by ...
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SWITCHING BETWEEN POWER MODES Switching from a higher to a lower power consumption mode is performed by writing an appropriate value to the Power Management Control Register (PMMSTCTL). Switching from a lower power consumption mode to the Ac- tive ...
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Software-Controlled Transition to Active Mode A transition from Power Save mode to Active mode can be accomplished by either a software method or a hardware wake-up event. The software method is to write the PMMSTCTL.PSM bit. ...
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HALT The Halt Mode bit indicates whether the de- vice is in Halt mode. If the WBPSM bit is clear and the device is in Power Save mode, writing 1 to the HALT bit causes the device to start the ...
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Multi-Input Wake-Up The Multi-Input Wake-Up (MIWU) module allows most gen- eral-purpose I/O port pins, certain peripheral pins (that do not share functionality with a GPIO port), and certain pe- ripheral events to break the system out of a low-power ...
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Table 36 lists the sources connected to the MIWU inputs. A source which is a GPIO port pin cannot be used unless it is enabled for use as an input, either by enabling an alternate function in which the pin ...
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MULTI-INPUT WAKE-UP REGISTERS Table 37 lists the MIWU registers. Table 37 Multi-Input Wake-Up Registers Name Address WKRPND1 FF C020h WKRPND2 FF C024h WKFPND1 FF C030h WKFPND2 FF C034h WKCLR1 FF C040h WKCLR2 FF C044h WKREN1 FF C000h WKREN2 FF ...
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Rising Edge Enable Register n (WKRENn) The WKRENn registers are 32-bit, read/write registers that enable a wake-up event when a rising edge is detected on the corresponding MIWU input. Bits 31:0 of WKREN1 cor- respond to MIWU inputs 31:0 ...
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Interrupt Control Register n (WKICTLn) The WKICTLn registers are 32-bit, read/write registers that provide 2-bit fields which select the MIWU interrupt chan- nels used by the associated MIWU channels. Each MIWU input can only activate one of four interrupt ...
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Input/Output Ports The CP3SP33 has 64 software-configurable general-pur- pose I/O pins (36 on the FBGA-144 package), organized into four ports, named Port E, Port F, Port G, and Port H. All 16 pins on Ports E, F, and G ...
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OPEN-DRAIN OPERATION A port pin can be configured to operate as an inverting open-drain output buffer this, software must clear the bit in the PxDOUT register and use the PxDIR bit to set the value of the ...
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In the descriptions of the port registers, the lower-case letter “x” represents the port designation, either For example, “PxDIR register” means any one of the port direc- tion registers: PEDIR, PFDIR, PGDIR, or PHDIR. All ...
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Port Alternate Function Register (PxALT) The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate function. Each port pin can be controlled independently. A clear bit in the alternate function register causes ...
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Table 39 Alternate Function Select Port PxALTS = 0 Pin (Device A) PG8 SRFS PG9 SCK PG10 SFS PG11 STD PG12 SRD PG13 SRCLK PG14 UART3 RXD3 PG15 UART3 TXD3 PH0 TIO1_4 PH1 SDA0 PH2 CAN0RX PH3 CAN0TX PH4 Reserved ...
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... LMX5252 and other RF transceiver chips For a detailed description of the interface to the LMX5252, consult the LMX5252 data sheet which is available from the National Semiconductor wireless group. National provides software libraries for using the Bluetooth LLC. Documenta- tion for the software libraries is also available from National Semiconductor ...
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RFSYNC In receive mode (data direction from the radio chip to the CP3SP33), the RFSYNC signal acts as the frequency cor- rection/DC compensation circuit control output to the radio chip. The RFSYNC signal is driven low throughout the cor- relation ...
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Figure 26 shows the serial interface protocol format. 15 Data[15: Header[2:0] R/W Figure 26. Serial Interface Protocol Format Data is transferred on the serial interface with the most sig- nificant bit (MSB) first. Write Operation When ...
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Write Operation On the LMX5252, a 32-bit register is loaded by writing to the same register address twice. The first write loads the high word (bits 31:16), and the second write loads the low word (bits 15:0). The two ...
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LMX5251 POWER-UP SEQUENCE To power-up a Bluetooth system based on the CP3SP33 and LMX5251 devices, the following sequence must be per- formed: 1. Apply VDD to the LMX5251. 2. Apply IOVCC and VCC to the CP3SP33. 3. The RESET_N ...
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LMX5252 POWER-UP SEQUENCE A Bluetooth system based on the CP3SP33 and LMX5252 devices has the following states: ! Off—When the LMX5252 enters Off mode, all configura- tion data is lost. In this state, the LMX5252 drives BPOR low. ! ...
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BLUETOOTH SLEEP MODE The Bluetooth controller is capable of putting itself into a sleep mode for a specified number of Slow Clock cycles. In this mode, the controller clocks are stopped internally. The only circuitry which remains active are ...
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BLUETOOTH GLOBAL REGISTERS Table 41 shows the memory map of the Bluetooth LLC glo- bal registers. Table 41 Memory Map of Bluetooth Global Registers Address – 0001 2080h 0001 20C8h Global LLC Configuration – 0001 20C9h 0001 20FFh 19.7 ...
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Telematics Codec The telematics codec provides dual input channels for voice recognition, telematics, voice-over-IP (VoIP), and Bluetooth applications, and it provides high-quality stereo output for music playback and voice DAC functions. The ADC has these features: ! Two differential ...
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CODEC DAC The stereo DAC operates in one of four oversampling modes (32×, 64×, 125×, or 128×), as selected in the DA- COSR field of the TCDCBASIC register. This allows a 12- MHz clock for 8, 16, 24, or ...
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PERIPHERAL BUS INTERFACE The codec is a slave device on the shared audio peripheral APB bus. As shown in Figure 37, the codec interface has four FIFOs, two read FIFOs for the two ADC channels and two write FIFOs ...
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FREEZE MODE When Freeze mode is entered, the codec will exhibit the fol- lowing behavior: ! The contents of the ADC and DAC FIFOs and the FIFO output data do not change. ! The DAC outputs are muted. 20.7 ...
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Codec Basic Configuration Register (TCDCBASIC) The TCDCBASIC register is a 16-bit read/write register that controls the basic operation of the codec. At reset, this reg- ister is cleared to 0000h MUTEL DACOSR DACSTMODE ADC2ON ...
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Codec DAC Status Register (TCDCDACSTATUS) The TCDCDACSTATUS register is a 16-bit, read-only regis- ter that indicates the status of the DAC FIFOs and the DAC analog output stage. After DAC operation is enabled in the TCDCDACCLK and TCDCBASIC registers, ...
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ADC1FIFO The ADC1 FIFO Status field indicates the cur- rent status of the ADC1 FIFO. After reset, the default mode for this field is to report the num- ber of empty words in the FIFO indicates 10h (empty). ...
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CLKPH The Clock Phase bit can be used to invert the phase of the output clock for use with non- standard digital microphones. 0 – Normal clock. 1 – Inverted clock. SIDETONEATTEN The Sidetone Attenuation field specifies the gain used ...
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MICMODE The Microphone Mode field configures the an- alog microphone input. 0 – Differential (TCMICnP and TCMICnN in- puts). 1 – Single-ended (TCMICnP input only). MICSEL The Microphone Select bit selects between the analog and digital microphone inputs. When a ...
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Codec DAC Clock Control Register (TCDCDACCLK) The TCDCDACCLK register is a 16-bit, read/write register that configures the DAC clock source. This register must only be programmed when the DAC is disabled. At reset, this register is cleared to 0000h. ...
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Codec FIFO Trigger Control Register (TCDCFIFO) The TCDCFIFO register is a 16-bit, read/write register that configures the events which assert DMA and interrupt re- quests. At reset, this register is cleared to 0000h ADC2FIFOTRIG ADC1FIFOTRIG 15 ...
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ADC2UP The ADC2 Power-Up bit enables an interrupt when ADC2 has powered up. 0 – ADC2 power-up interrupt disabled. 1 – ADC2 power-up interrupt enabled. DACUP The DAC Power-Up bit enables an interrupt when the stereo DAC has powered up. ...
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Codec Right Channel DAC Data Register (TCDCRIGHT) The TCDCRIGHT register is a 16-bit, read/write register used to load a word into the right-channel DAC FIFO. After reset, this register is cleared to 0000h 15 RIGHTDATA 20.10.17 Codec Debug Register ...
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USAGE NOTES The telematics codec is designed for maximum flexibility, this section gives an overview of recommended system set- ups for different applications. 20.11.1 In-Car Bluetooth Telephony In this mode, the codec acts as a bridge between a Blue- ...
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USB Controller The dual-role USB controller may be used as either the host or the peripheral in point-to-point communications with an- other USB device. The USB controller is a peripheral on the CPU core AHB bus. An on-chip USB ...
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MODES OF OPERATION The USB controller has two main modes of operation: ! Peripheral Mode —the USB controller encodes, decodes, checks, and directs all USB packets sent and received. IN transactions are handled through the device’s Tx FIFOs, and ...
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USB CONTROLLER REGISTER SET The USB controller common registers affect all endpoints. In addition, for each endpoint there is an endpoint-specific register bank. There is an indexed addressing mechanism for accessing the endpoint-specific register banks, and there are also ...
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Function Address Register (FADDR) The FADDR register is an 8-bit, read/write register that holds the function address. When the USB controller is in Host mode, this register should be loaded with the value sent in a SET_ADDRESS command during ...
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Interrupt Register for Endpoint 0 and Transmit Endpoints (INTRTX) The INTRTX register is a 16-bit, read-only register that indi- cates which interrupts are currently asserted for Endpoint 0 and the Transmit Endpoints 1, 2, and 3. Bits for endpoints ...
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Interrupt Register for USB Controller (INTRUSB) The INTRUSB register is an 8-bit, read-only register that in- dicates which interrupts are currently asserted for the USB controller. All asserted interrupts are cleared when this reg- ister is read. After reset, ...
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VBUSERROR The VBUS Error bit enables an interrupt when VBUS drops below the VBUS Valid threshold during a session. This bit is only valid when the USB controller device. 0 – No interrupt enabled. 1 – Interrupt ...
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Endpoint 0 Control and Status Register (CSR0) The CSR0 register is a 16-bit, read/write register that pro- vides control and status bits for Endpoint 0. It has different formats in Peripheral and Host modes. After reset, this reg- ister ...
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SETUPPKT The Setup Packet bit is set by software at the same time the TXPKTRDY bit is set, to select a SETUP token instead of an OUT token for the transaction. 0 – OUT token selected. 1 – SETUP token ...
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Transmit Control and Status Register (TXCSR) The TXCSR register is a 16-bit, read/write register that pro- vides control and status bits for the associated endpoint (ex- cept Endpoint 0). It has different formats in Peripheral and Host modes. After ...
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Host Mode Format Reserved TXPKTRDY The Transmit Packet Ready bit is set by soft- ware after loading a data packet into the FIFO. The bit is cleared automatically when the ...
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Receive Maximum Packet Size Register (RXMAXP) The RXMAXP register is a 16-bit, read/write register that specifies the maximum amount of data that can be trans- ferred through the selected receive endpoint in a single frame. The value is subject ...
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FLUSHFIFO The FLUSHFIFO bit is written with 1 to flush the receive FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. The FLUSHFIFO bit has no effect unless RXPK- TRDY bit is set. If double-buffering is enabled, ...
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FLUSHFIFO The FLUSHFIFO bit is written with 1 to flush the receive FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. The FLUSHFIFO bit has no effect unless RXPK- TRDY bit is set. If double-buffering is enabled, ...
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Transmit Interval Register (TXINTERVAL) The TXINTERVAL register is an 8-bit, read/write register that specifies the polling interval for the currently selected transmit endpoint, for Interrupt and Isochronous endpoints. For Bulk endpoints, this register specifies the number of frames after ...
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USB Transceiver Status Register (VSTATUS) The VSTATUS register is an 8-bit, read-only register that re- turns the data in the addressed USB transceiver control reg- ister. At reset, this register is cleared to 00h. 7 VSTATUS VSTATUS The VSTATUS ...
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Dual CAN Interfaces Each CAN interface contains a Full CAN class, CAN (Con- troller Area Network) serial bus interface for low/high speed applications. It supports reception and transmission of ex- tended frames with a 29-bit identifier, standard frames with ...
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BASIC CAN CONCEPTS This section provides a generic overview of the basic con- cepts of the Controller Area Network (CAN). The CAN protocol is a message-based protocol that allows 11 a total of 2032 (2 - 16) different messages ...
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The CAN protocol allows several transmitting modules to start a transmission at the same time as soon as they detect the bus is idle. During the start of transmission, every node monitors the bus line to detect whether its message ...
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Data Length Code (DLC) The DLC field indicates the number of bytes in the data field. It consists of four bits. The data field can be of length zero. The admissible number of data bytes for a data frame rang- ...
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A CAN data frame consists of the following fields: ! Start of Frame (SOF) ! Arbitration Field + Extended Arbitration ! Control Field ! Data Field ! Cyclic Redundancy Check Field (CRC) Arbitration Field 11 d IDENTIFIER 10 ... 0 ...
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Error Frame As shown in Figure 48, the Error Frame consists of the error flag and the error delimiter bit fields. The error flag field is built up from the various error flags of the different nodes. Therefore, its length ...
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ANY FRAME INT = Intermission Suspend Transmission is only for error passive nodes. 22.2.4 Error Types Bit Error A CAN device which is currently transmitting also monitors the bus. If the monitored bit value ...
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Error Active An error active unit can participate in bus communication and may send an active (“dominant”) error flag. Error Warning The Error Warning state is a sub-state of Error Active to in- dicate a heavily disturbed bus. A CAN ...
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Bit Time Logic In the Bit Time Logic (BTL), the CAN bus speed and the Synchronization Jump Width can be configured by software. The CAN module divides a nominal bit time into three time segments: synchronization segment, time segment ...
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Bus Signal CAN Clock PREVIOUS A BIT PREVIOUS A BIT Bus Signal CAN Clock PREVIOUS BIT PREVIOUS BIT 22.2.7 Clock Generator The CAN prescaler (PSC) is shown is Figure 55. It divides the CKI input clock by the value defined ...
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BASIC-CAN path. For reception of data frame or remote frames, a CAN mod- ule follows a “receive on first match” rule which means that a given message is only ...
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With this lock function, software has the capability to save several messages with the same identifier or same identifier group into more than one buffer. For ex- ample, a buffer with the second highest priority will receive ...
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All contents of the hidden receive buffer are always copied into the respective receive buffer. This includes the received message ID as well as the received Data Length Code (DLC); therefore when some mask bits are set to don’t care, ...
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Read buffer Read CNSTAT Yes RX_READY? No Yes RX_BUSYx? No Interrupt Entry Point RX_OVERRUN? Write RX_READY Read buffer (id/data/control) Read CNSTAT Yes RX_BUSYx? No Yes RX_FULL or RX_OVERRUN? No Clear RX_PND Exit Figure 62. Buffer Read Routine (BUFFLOCK Disabled) The ...
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CNSTAT status section will be 0101b, as the buffer was RX_FULL (0100b) before. After finally reading the last re- ceived message, the CPU can reset the buffer to RX_READY. 22.6 TRANSMIT STRUCTURE To transmit a CAN message, software must configure ...
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TXPRI value and the 4-bit buffer number (0...14) as shown below. The lowest resulting num- ber results in the highest transmit priority TXPRI Table 53 shows the transmit priority configuration if ...
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TX Buffer States The transmission process can be started after software has loaded the buffer registers (data, ID, DLC, PRI) and set the buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR, or TX_ONCE_RTR. When the CPU writes TX_ONCE, the buffer ...
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Highest Priority Interrupt Code To reduce the decoding time for the CIPND register, the buffer interrupt request with the highest priority is placed as interrupt status code into the IST[3:0] section of the CSTP- ND register. Each of the ...
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MEMORY ORGANIZATION Each CAN module occupies 288 words in the memory ad- dress space. This space is organized as 15 banks of 16 words per bank (plus one 16-word reserved bank) for the message buffers and 28 words (plus ...
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CAN CONTROLLER REGISTERS Table 57 lists the registers for the two CAN modules (CAN0 and CAN1). Table 57 CAN Controller Registers Name Address See CNSTAT Table 56 CGCR0 FF BA00h CGCR1 FF BE00h CTIM0 FF BA04h CTIM1 FF BE04h ...
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Table 58 Buffer Status Section of the CNSTAT Register ST3 (DIR) ST2 ST1 ...
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PRI The Transmit Priority Code field holds the software-defined transmit priority code for the message buffer. DLC The Data Length Code field determines the number of data bytes within a received/trans- mitted frame. For transmission, these bits need to be ...
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Storage of Messages with Less Than 8 Data Bytes The data bytes that are not used for data transfer are “don’t cares”. If the object is transmitted, the data within these bytes will be ignored. If the object is ...
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Storage of Remote Messages During remote frame transfer, the buffer registers DATA0– DATA3 are “don’t cares” remote frame is transmitted, the contents of these registers are ignored remote Buffer Address 15 14 Register BASE + ...
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CAN Global Configuration Register n (CGCRn) The CGCRn register is a 16-bit, read/write register used to: ! Enable/disable the CAN module. ! Configure the BUFFLOCK function for the message buff- er 0..14. ! Enable/disable the time stamp synchronization. ! ...
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Sequence of Data Bytes on the Bus ID Data1 Storage of Data Bytes in the Buffer Memory Setting the DDIR bit will cause the direction of the data stor- age to be reversed — the last byte received is stored ...
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INTERNAL If the Internal function is enabled, the CANnTX and CANnRX pins of the CAN mod- ule are internally connected to each other. This feature can be used in conjunction with the LOOPBACK mode. This means that the CAN module ...
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TSEG1 The Time Segment 1 field configures the length of the Time Segment 1 (TSEG1 not recommended to configure the time seg- ment smaller than 2 time quanta. (see Table 65). Table 65 Time Segment ...
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CAN Basic Mask Register n (BMSKBn/BMSKXn) The BMSKBn and BMSKXn registers allow masking the buffer 14, or “don’t care” the incoming extended/standard identifier bits, RTR/XRTR, and IDE. Throughout this docu- ment, the two 16-bit registers BMSKBn and BMSKXn are ...
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CAN Interrupt Clear Register n (CICLRn) The CICLRn register bits individually clear CAN interrupt pending flags caused by the message buffers and from the Error Management Logic. Do not modify this register with in- structions that access the register ...
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CAN Error Counter Register n (CANECn) The CANECn register reports the values of the CAN Re- ceive Error Counter and the CAN Transmit Error Counter REC 0 R REC The CAN Receive Error Counter field reports ...
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DRIVE The Drive bit shows the output value on the CANnTX pin at the time of the error. Note that a receiver will not drive the bus except during ACK and during an active error flag. 22.10.17 CAN Timer Register ...
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Table 71 CAN Module Internal Timing Cycle Task Count Copy hidden buffer to receive 17 message buffer Update status from TX_RTR 3 to TX_ONCE_RTR Schedule a message for 2 transmission The critical path derives from receiving a remote frame, which ...
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USAGE NOTES Under certain conditions, the CAN module receives a frame sent by itself, even though the loopback feature is disabled. Two conditions must be true to cause this malfunction transmit buffer and at least one receive ...
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Analog to Digital Converter The ADC provides the following features: ! 10-input analog multiplexer ! 10 single-ended channels or 5 differential channels ! External filtering capability ! 12-bit resolution with 10-bit accuracy Figure 73. Analog to Digital Converter Block ...
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The output of the Input Multiplexer is available externally as the MUXOUT0 and MUXOUT1 signals. In single-ended mode, only MUXOUT0 is used. In differential mode, MUXOUT0 is the positive side and MUXOUT1 is the nega- tive side. The MUXOUT0 and ...
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FREEZE MODE When Freeze mode is entered, the ADC will exhibit the fol- lowing specific behavior: ! The automatic clear-on-read function of the result regis- ter (ADCRESLT) is disabled. ! The FIFO is updated as usual, and an interrupt ...
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NREF_CFG The Negative Voltage Reference Configura- tion field specifies the source of the ADC neg- ative voltage reference, as shown below: NREF_CFG MUXOUTEN The MUXOUT Enable bit controls whether the output of the Input Multiplexer is ...
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ADC Conversion Control Register (ADCCNTRL) The ADCCNTRL register is a 16-bit, read/write register that specifies the trigger conditions for an ADC conversion. After reset, the register is cleared Reserved POL The ASYNC Polarity bit specifies the polarity ...
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ADC Result Register (ADCRESLT) The ADCRESLT register is a 16-bit, read-only register that includes the software-visible end of a 4-word FIFO. Conver- sion results are loaded into the FIFO from the ADC and un- loaded when software reads the ...
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Advanced Audio Interface The Advanced Audio Interface (AAI) provides a serial syn- chronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asyn- chronously with respect to each other. Each path uses ...
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Normal Mode In normal mode, each rising edge on the frame sync signal marks the beginning of a new frame and also the beginning of a new slot. A slot does not necessarily occupy the entire frame. (A frame ...
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Each slot may be configured individu- ally. Figure 76 shows the frame timing while operating in network mode with four slots per frame, slot 1 assigned to the inter- face, and a long frame sync interval. ...
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Figure 78. Accessing Three Devices in Network Mode Because four of the six AAI DMA requests can be handled by either the CPU or DSP DMA controllers, these DMA re- quests are passed through the Audio Subsystem Controller (ASC), which ...
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Interrupts The interrupt logic of the AAI combines up to four interrupt sources and generates one interrupt request signal to the Interrupt Control Unit (ICU). The four interrupt sources are FIFO Overrun - AISCR.RXEIP = 1 ! ...
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In this case, the new data in the ARSR will not be copied into the FIFO and the RWP will not be incremented. A receive FIFO overrun is indicated by the RXO bit in the Audio Interface ...
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COMMUNICATION OPTIONS 24.6.1 Data Word Length The word length of the audio data can be selected to be ei- ther bits. In 16-bit mode, all 16 bits of the transmit and receive shift registers (ATSR and ...
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IOM-2 Mode The AAI can operate in a special IOM-2 compatible mode to allow to connect to an external ISDN controller device. In this IOM-2 mode, the AAI can only operate as a slave, i.e. the bit clock and ...
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Freeze Mode When the Freeze mode is entered, the audio interface ex- hibits the following behavior: ! The receive FIFO or receive DMA registers are not up- dated with new data. ! The receive status bits (RXO, RXE, RXF, ...
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Audio Receive FIFO Register (ARFR) The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), ...
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Audio Global Configuration Register (AGCR) The AGCR register controls the basic operation of the inter- face. The APB bus master has read/write access to the AGCR register. After reset, this register is clear IEBC ...
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AAIEN The AAI Enable bit controls whether the Ad- vanced Audio Interface is enabled. When the AAI is disabled, all AAI registers remain ac- cessible. 0 – AAI module disabled. 1 – AAI module enabled. CLKEN The Clock Enable bit ...
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Audio Receive Status and Control Register (ARSCR) The ARSCR register is used to control the operation of the receiver path of the audio interface. It also holds bits which report the current status of the receive FIFO. The APB ...
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Audio Transmit Status and Control Register (ATSCR) The ATSCR register controls the basic operation of the in- terface. It also holds bits which report the current status of the audio communication. The APB bus master has read/ write access ...
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Audio Clock Control Register (ACCR) The ACCR register is used to control the bit timing of the au- dio interface. After reset, this register is clear. 7 FCPRS 15 BCPRS CSS The Clock Source Select bit selects one out ...
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USAGE EXAMPLE The following example shows the AAI being used to inter- face to two single-channel codecs. The interface has the fol- lowing characteristics: ! Synchronous mode ! 8-bit data word ! Network mode with 4 slots per frame ...
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I S Interface 2 The Inter-IC Sound (I S) bus is a popular 3-wire serial bus for interface to audio chips, such as codecs. This is a simple data interface, without any form of address or device selec- ...
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Figure 88 shows the timing of a right-justified data transfer. 25.1 INTERRUPTS AND DMA Programmable thresholds are provided for the transmit and receive FIFOs to assert interrupt or DMA requests when the transmit FIFO can accept new data or the ...
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I S Clock Register (I2SCLK) The I2SCLK register is a 32-bit, read/write register that con- trols clock configuration, master/slave select, and word length. Before enabling master mode (MS bit = 1), the CLKSEL, CLKDIV, and WSRES fields must ...
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RXLI The Left Channel Receive Interrupt Enable bit enables an interrupt request when the number of empty words in the left receive FIFO is equal to or less than the receive FIFO thresh- old specified in the RXFIFOTHRES field. The ...
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TXLI The Left Channel Transmit Interrupt Enable bit enables an interrupt request when the number of filled words in the left transmit FIFO is equal to or less than the transmit FIFO threshold specified in the TXFIFOTHRES field. The sta- ...
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I S Status Register (I2SSTAT) The I2SSTAT register is a 32-bit, read/write register that in- 2 dicates the status module and clears interrupt re- quests. The TXRIRQ, TXLIRQ, TXERIRQ, RXRIRQ, RXLIRQ, and RXERIRQ bits are ...
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RXSTATUSR The Receive FIFO Status Right Channel field indicates the current fill level of the right chan- nel receive FIFO. This field is not sticky overrun condition may disappear before soft- ware reads this field. Use the RXERIRQ ...
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Dual CVSD/PCM Conversion Modules The CVSD/PCM modules perform conversion between CVSD data and PCM data, in which the CVSD encoding is that used in Bluetooth communication and the PCM encod- ing may be 8-bit µ-Law, 8-bit A-Law, or 13-bit ...
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CVSD CONVERSION The CVSD/PCM converter module transforms either 8-bit logarithmic or 13- to 16-bit linear PCM samples at a fixed rate of 8 ksps. The CVSD to PCM conversion format must be specified by the CVSDCONV control bits in ...
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Because the PCM I/O interrupt requests can be handled by either the CPU or DSP interrupt controllers, the interrupt re- quests are passed through the Audio Subsystem Controller (ASC), which is programmed to route them to the interrupt controller. To ...
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CVSD/PCM AUDIO DATA FLOW CVSD and PCM data can be transferred to and from the CVSD/PCM modules using DMA channels. Alternatively, CVSD data can be transferred to and from the CVSD/PCM modules by software directly accessing the FIFOs, through ...
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With an audio sample rate of 8 ksps, ATDR0 will request a DMA transfer every 125 ms (every 1500 CPU clock cycles MHz PCLK Clock rate). CVSD Transmit/Receive Paths The CVSD/PCM modules operate in their fixed-rate mode ...
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The CVSD/PCM module requests a DMA transfer each time a new PCM sample is available in PCMOUT0. If PCMOUT0 is assigned to device A and the DIR bit in the DMA channel control register is clear, the DMA controller reads ...
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CVSD/PCM CONVERTER REGISTERS Table 76 lists the CVSD/PCM registers. Table 76 CVSD/PCM Registers Name Address CVSDIN0 FF 4800h CVSDIN1 FF 4C00h CVSDOUT0 FF 4804h CVSDOUT1 FF 4C04h PCMIN0 FF 4808h PCMIN1 FF 4C08h PCMOUT0 FF 480Ch PCMOUT1 FF 4C0Ch ...
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Logarithmic PCM Data Output Register n (LOGOUTn) The LOGOUTn registers are 8-bit, read-only registers. They hold logarithmic PCM data that has been converted from lin- ear PCM data. After reset, the LOGOUT registers are clear. 7 LOGOUT 26.12.7 Linear ...
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PCMCONV The PCM to PCM Conversion Format bit se- lects the PCM format for PCM/PCM conver- sions. 0 – Linear PCM <-> 8-bit µ-Law PCM 1 – Linear PCM <-> 8-bit A-Law PCM RESOLUTION The Linear PCM Resolution field specifies ...