21143TD Intel, 21143TD Datasheet - Page 18

• Manufacturer Part Number: 21143TD
• Manufacturer: Intel

Specifications of 21143TD

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

21143
14
stop_l
tck
tdi
tdo
tms
tp_rd–
tp_rd+
tp_td–
tp_td– –
tp_td+
tp_td+ +
trdy_l
vcap_h
vdd
vddac
vdd_clamp
vss
xtal1
Signal
Type
I/O
I/O
O
O
O
O
O
P
P
P
P
I
I
I
I
I
I
I
Table 4. Functional Description of 21143 Signals (Sheet 5 of 6)
1, 2, 8, 18, 26,
36, 37, 46, 54,
67, 72, 73, 79,
38, 42, 53, 63,
71, 74, 83, 94,
104, 116, 126,
95, 107, 125,
3, 17, 30, 35,
Pin Number
136, 141
109, 111
110
144
106
56
11
13
14
12
10
52
20
9
5
4
6
7
Stop indicator indicates that the current target is requesting the bus
master to stop the current transaction.
The 21143 responds to the assertion of stop_l when it is the bus
master, either to disconnect, retry, or abort.
JTAG clock shifts state information and test data into and out of the
21143 during JTAG test operations.
JTAG data in is used to serially shift test data and instructions into the
21143 during JTAG test operations.
JTAG data out is used to serially shift test data out of the 21143
during JTAG test operations.
JTAG test mode select controls the state operation of JTAG testing in
the 21143.
Twisted-pair negative differential receive data from the twisted-pair
lines.
Twisted-pair positive differential receive data from the twisted-pair
lines.
Twisted-pair negative differential transmit data. The positive and
negative differential transmit data outputs are combined resistively
outside the 21143 with equalization to compensate for intersymbol
interference on the twisted-pair medium.
Twisted-pair positive differential transmit data. The positive and
negative differential transmit data outputs are combined resistively
outside the 21143 with equalization to compensate for intersymbol
interference on the twisted-pair medium.
Target ready indicates the target agent’s ability to complete the
current data phase of the transaction.
A data phase is completed on any clock when both trdy_l and irdy_l
are asserted. Wait cycles are inserted until both irdy_l and trdy_l are
asserted together.
When the 21143 is the bus master, target ready is asserted by the
bus slave on the read operation, which indicates that valid data is
present on the ad lines. During a write cycle, it indicates that the
target is prepared to accept data.
3.3-V supply input. These pins should be connected to the auxiliary
power, if such power exists. Otherwise, these pins should be
connected to the main power.
Supplies +5-V or +3.3-V reference for clamp logic.
This pin is also used to identify the lack of main power when the
auxiliary power is on. This pin should be connected to the main
power.
Ground pins.
20-MHz crystal input, or crystal oscillator input.This pin should always
be provided with a clock.
Capacitor input for analog phase-locked loop logic.
Supplies +3.3-V input for analog phase-locked loop logic.
If the JTAG port is unused, this pin should be connected to vss.
Description
Preliminary
Datasheet