CY7C4255-25AC Cypress Semiconductor Corp, CY7C4255-25AC Datasheet - Page 2

• Manufacturer Part Number: CY7C4255-25AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4255-25AC

• Density: 128Kb
• Word Size: 18b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: TQFP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06004 Rev. *C
Pin Configurations
Functional Description
The CY7C4255/65 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost
Empty, Half Full, Almost Full, and Full. The Half Full flag
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
Package
Density
CC1
) (mA)
64-pin TQFP,
CY7C4255
8K x 18
STQFP
Commercial
Industrial
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(continued)
15
14
13
12
11
10
9
5
1
8
7
6
4
3
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-pin TQFP,
CY7C4265
16K x18
7C4255/65-10
STQFP
100
0.5
10
45
50
CY7C4255
CY7C4265
8
3
8
TQFP/STQFP
Top View
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous if the V
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
7C4255/65-15
66.7
10
15
10
45
50
4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
Q
GND
Q
Q
V
Q
Q
GND
Q
Q
Q
Q
GND
Q
V
CC
CC
14
13
12
11
10
9
8
7
6
5
4
7C4255/65-25
40
15
25
15
45
50
6
1
CC
/SMODE is tied to V
CY7C4255
CY7C4265
7C4255/65-35
Page 2 of 22
28.6
35
45
50
20
20
7
2
SS
.
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