PEF80902HV1.1XT Infineon Technologies, PEF80902HV1.1XT Datasheet - Page 57

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PEF80902HV1.1XT

Manufacturer Part Number
PEF80902HV1.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF80902HV1.1XT

Lead Free Status / Rohs Status
Compliant
3.2
Test loopbacks are specified by the national PTTs in order to facilitate the location of
defect systems. Four different loopbacks are defined. The position of each loopback is
illustrated in
Figure 17
Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled
locally on the remote side. All four loopback types are transparent. This means all bits
that are looped back will also be passed onwards in the normal manner. Only the data
looped back internally is processed; signals on the receive pins are ignored. The
propagation delay of actually looped B and D channels data must be identical in all
loopbacks.
3.2.1
The following loopback type belongs to the loopback-#2 category:
• complete loopback (B1,B2,D), in a downstream device
Normally loopback #2 is controlled by the exchange. The maintenance channel is used
for this purpose.
3.2.1.1
When receiving the request for a complete loopback, the U transceiver passes it on to
the S-bus transceiver. This is achieved by issuing the C/I-code AIL in the “Transparent”
state or C/I = ARL in states different than “Transparent”
Data Sheet
S-BUS
Layer-1 Controller
Layer-1 Controller
S-Transceiver
Layer 1 Loopbacks
Loopback No.2
Complete Loopback
Loop 2
Figure
Test Loopbacks
PBX or TE
IOM
IOM
IOM-2
NT
17.
®
®
-2
-2
U-Transceiver
U-Transceiver
U-Transceiver
Loop 2
Loop 2
Loop 2
Loop 3
U
U-Transceiver
Loop 1 A
49
Repeater
IOM
(optional)
®
-2
U-Transceiver
Operational Description
U
U-Transceiver
Exchange
Loop 1
loop_2b1q.emf
PEF 80902
IOM
2001-11-12
®
-2

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