W66910CD Winbond Electronics, W66910CD Datasheet
W66910CD
Specifications of W66910CD
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W66910CD Summary of contents
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TE Mode ISDN S/T-Controller with Microprocessor W66910 PCI ISDN S/T-Controller W66910 Interface Data Sheet -1 - Publication Release Date: Data Sheet Feb,2001 Revision 1.0 ...
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The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes for W66910-based system design. Winbond assumes no ...
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TABLE OF CONTENTS 1. GENERAL DESCRIPTION................................................................................................................................................. 8 2. FEATURES............................................................................................................................................................................ 8 3. PIN CONFIGURATION ..................................................................................................................................................... 9 4. PIN DESCRIPTION........................................................................................................................................................... 11 5. SYSTEM DIAGRAM AND APPLICATIONS................................................................................................................ 13 6. BLOCK DIAGRAM ........................................................................................................................................................... 14 7. FUNCTIONAL DESCRIPTIONS..................................................................................................................................... 15 7 ................................................................................................................................................... 15 ...
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HDLC HIP ONTROL AND CH CONTROLLER 8.1.1 D_ch receive FIFO D_RFIFO Read Address 00H................................................................................................... 44 8.1.2 D_ch transmit FIFO D_XFIFO Write Address 01H ................................................................................................ 44 8.1.3 D_ch command register D_CMDR Write Address 02H ............................................................................................ 45 8.1.4 ...
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B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 25H......................................................... 69 8.2.7 B1_ch Status Register B1_STAR Read Address 26H ................................................................................................ 69 8.2.8 B1_ch Address Mask Register 1 B1_ADM1 Read/Write Address 27H....................................................................... 70 8.2.9 B1_ch Address Mask Register 2 B1_ADM2 Read/Write ...
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LIST OF FIGURES FIG.3.1 W66910 PIN CONFIGURATION - INTEL BUS MODE..................................................................................................9 FIG.3.2 W66910 PIN CONFIGURATION - MOTOROLA BUS MODE .....................................................................................10 FIG.5.1 W66910 INTERFACE CIRCUIT FOR ISDN EMBEDED APPLICATION ....................................................................13 FIG.6.1 W66910 FUNCTIONAL BLOCK DIAGRAM ...............................................................................................................14 FIG.7.1 FRAME STRUCTURE AT S/T ...
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LIST OF TABLES TABLE 4.1 W66910 PIN DESCRIPTIONS ................................................................................................................................11 TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE...........................................................................................20 TABLE 7.2 LAYER 1 COMMAND CODES ..............................................................................................................................22 TABLE 7.3 LAYER 1 INDICATION CODES ............................................................................................................................22 TABLE 7.4 D PRIORITY CLASSES ..........................................................................................................................................26 TABLE 7.5 D PRIORITY ...
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GENERAL DESCRIPTION The Winbond's single chip TE mode ISDN S/T interface controller (W66910 all-in-one device suitable for ISDN Internet access. Three HDLC controllers are incorporated in the chip, one for D channel and the other two for ...
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PIN CONFIGURATION RST# 81 VSSD 82 VDDD 83 84 CLK VSSB 88 89 VDDB 100 FIG.3.1 W66910 PIN CONFIGURATION - INTEL BUS MODE ...
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RST ...
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PIN DESCRIPTION TABLE 4.1 W66910 PIN Notation : The suffix "#" indicates an active LOW signal. In Intel or Motorola bus mode, all unspecified pins must be left unconnected. Pin Name Pin Number CLK 84 AD7-0 38,39,40,41,44,45 ,46,47 CS# ...
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SR1 49 SR2 50 SX1 54 SX2 55 XTAL1 56 XTAL2 57 TESTP 61 TOUT2 20 XINTIN0 52 XINTIN1 53 IO10-IO0 79,78,77,29,28, 27,26,4,3,2,1 XAD7-XAD0 29,28,27,26, 4,3,2,1 XALE 77 XRDB 78 XWRB 79 VDDD 17,58,67,83 VDDA 51 VDDB 6,32,43,89 VSSD 16,59,68,82 ...
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SYSTEM DIAGRAM AND APPLICATIONS Typical applications include : - ISDN TA, Router or other embedded application The all-in-one characteristic of W66910 makes it excellent for ISDN embeded application. W66910 integrates three HDLC controllers in the chip and interfaces to ...
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BLOCK DIAGRAM The block diagram of W66910 is shown in Figure 6.1 4-wire S/T GCI Bus Crystal/Oscillator (7.68 MHz) POTS circuit FIG.6.1 W66910 FUNCTIONAL BLOCK DIAGRAM B2 2B+D B1 Line Serial Transceiver Interface & Bus D AMI/BIN (SIB) B-channel ...
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FUNCTIONAL DESCRIPTIONS 7.1 Main Block Functions The functional block diagram of W66910 is shown in Fig.6.1. The main function blocks are : - Layer 1 function according to ITU-T I.430 - Serial Interface Bus (SIB channel switching ...
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Layer 1 Functions Descriptions The layer 1 functions includes : - Transmitter/Receiver which conform to the electrical specifications of ITU-T I.430 - Receiver clock recovery and timing generation - Output phase delay (deviation) compensation - Layer 1 activation/deactivation procedures ...
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bits offset ...
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W66910 TR TE (a) Point-to-point configuration TR W66910 TE1 (b) Short passive bus configuration 50m TR W66910 . . . . . TE1 (c) Extended passive bus configuration FIG.7.2 W66910 WIRING CONFIGURATION IN TE APPLICATIONS W66910 PCI ISDN S/T-Controller 1000 ...
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The transmitter and receiver are implemented by differential circuits to increase signal to noise ratio (SNR). The nominal differential line pulse amplitude at 100 transmitter and receiver for voltage level translation and DC isolation. To meet the electrical characteristic requirements ...
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After hardware reset, the receiver may enter power down state in order to save power consumption. In this state, the internal clocks are turned off, but the analog level detector is still active to detect signal coming from the S ...
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This state is identical to "F3 Deactivated without clock" except the internal clocks are enabled. The state is entered by the ECK command. The clocks are enabled approximately 0 after the ECK command, depending on the ...
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Send Single Pulses A 2 KHz , isolated pulse with alternating polarities is sent. Layer 1 Reset A layer 1 reset command forces the transmission of INFO 0 and disables the S line awake detector. Thus activation from NT is ...
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F5. Note that the command code writtern by the microprocessor in CIX register and indication code written by layer 1 in CIR register are transmitted repeatedly until a new code is written. W66910 PCI ISDN S/T-Controller -23 - Publication Release ...
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F4 Await. Signal AR8/ ^i0 F5 Ident. Input i4 1) ^RST LD 2) any i0 i2 Lost F6 Synchronized Framing 1) ^RST ARD Activated AR8/10 AI8/ Lost i4 Framing ...
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Reset RST RST Ignored ECK Send Cont. Pulses SCP SCP Ignored Send Sing. Pulses SSP SSP Ignored 2) Y Note : 1. RST can be issued at any state, while SCP, SCZ and EAL can be issued ...
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D Channel Access Control The D channel access control includes collision detection and priority management. The collision detection is always enabled. The priority management procedure as specified in ITU-T I.430 is fully implemented in W66910. A collision is detected ...
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FAinfA_1fr This test checks if TE does not lose frame alignment on receipt of one bad frame. The pattern for the bad frame is defined as IX_96 kHz. This pattern consists of alternating pulses at 96 kHz during the ...
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Device Settings W66910 k =2 7.2.5.6 FAinfD_kfr This is to test the number k of IX_I4noflag frames necessary for loss of frame alignment. Device Settings W66910 7.2.5.7 Faregain This is to test the number m of good ...
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The multiframe synchronization can be disabled by setting MFD bit in the D_MODE register. - According to I.430 Recommendation, the S/Q channel can be used as operation and maintenance signalling channel. At transmitter, a S/Q code for a message ...
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Digital loop via DLP bit in D_MODE register: In the layer 2 block, the transmitted 2B+D data are internally looped (from HDLC transmitter to HDLC receiver), and in the PCM ports, the transmitted B channels are internally looped (from ...
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Serial Interface Bus The 192 kbps S/T interface signal consists of two B channels (64 kbps each), one D channel (16 kbps) and other control signals. The multiplexing/demultiplexing functions are carried out in the Serial Interface Bus (SIB) block. ...
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PXC PXC PXC PXC For example, to switch Layer1-B1 to/from PCM2/GCI_B2 : First look at Layer1-B1 receive table, we find ...
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PCM Port There are two PCM ports in W66910. Data is transmitted/ received when PFCK1/PFCK2 is HIGH. The frame synchronization clocks (PFCK1-2) are 8 kHz and the bit synchronization clock (PBCK) is 1.536 MHz. 7.6 D Channel HDLC Controller ...
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D Channel Message Transfer Modes The D channel HDLC controller operates in transparent mode. Chracteristics: - Receive frame address recognition - Address comparison maskable bit-by-bit - Flag generation / deletion - Zero bit insertion/ deletion - Frame Check Sequence ...
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FIFO. The D_RME interrupt indicates the last segment of a message or a message with length 64 bytes has been received. The length of data is less than or equal to ...
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After the microprocessor has issued the XME command, the successful termination of transmission is indicated by an D_XFR interrupt. The inter-frame time fill pattern must be all 1's, according to ITU-T I.430. Collisions which occur on the D channel of ...
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In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC check is indicated in Bn_STAR: CRCE bit. The data between opening flag and CRC field (not included) is stored in receive FIFO. Two ...
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The inter-frame time fill pattern can be programmed to 1's or flags. During the frame transmission, the microprocessor reaction time for the XFR interrupt depends on the FIFO threshold setting and B channel data rate. For example ...
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Octet 2 Octet 3 Octet 4 Octet DD,DU : 768 kbits/s FSC : 8 kHz DCL : 1536 kHz FIG 7.8 GCI MODE CHANNEL STRUCTURE GCI slave mode: connects to U transceiver such as ...
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The microprocessor may either enforce a 1 (idle state setting the control bit MRC or MXC (MOCR register enable the control of these bits internally by the W66910 according to the Monitor channel ...
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In application with POTS connection, the peripheral devices such as CODEC, DTMF and SLIC can be directly controlled by W66910, therefore reduce the IO requirement of microprocessor. The peripheral control function includes timer, interrupt inputs and programmable IO. There are ...
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REGISTER DESCRIPTIONS Note : For all the internal registers, only byte access is allowed in all cases. 8.1 Chip Control and D_ch HDLC controller TABLE 8.1 REGISTER ADDRESS MAP: CHIP CONTROL AND D CHANNEL HDLC Section Offset Access Register ...
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R/W GCR 8.1.33 3D R/W XDATA1 8.1.34 3E R/W XDATA2 8.1. MO1R 8.1.36 41 R/W MO1X 8.1.37 42 R_clear MO1I 8.1.38 43 R/W MO1C 8.1. IC1R 8.1.40 45 R/W IC1X 8.1. IC2R ...
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Offset R/W Name CIR SCC 17 R/W CIX SQR XIND1 19 R/W SQX 0 1A R/W PCTL OE5 1B R MO0R 1C R/W MO0X 1D R_clr MO0I 1E R/W MO0C 0 1F R/W GCR ...
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D_ch command register Value after reset: 00H RACK RRST 0 STT1 RACK Receive Acknowledge After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to ...
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Setting this bit activates the D_ch HDLC receiver. This bit can be read. The receiver must be in active state in order to receive data. XACTB Transmitter Active Resetting this bit activates the D_ch HDLC transmitter. This bit can be ...
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After writing this register, STT1 bit in D_CMDR register must be set to start the timer. This register can be read only after the timer has been started. The read value indicates the timer's current count value. In case layer ...
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B2_EXI B2_ch Extended Interrupt This bit indicates that at least one interrupt bit has been set in B2_EXIR register. Note : A read of the ISTA register clears all bits except D_EXI, B1_EXI and B2_EXI bits. D_EXI bit is cleared ...
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This bit is set when at least one bit is set in GCI_EXIR register. ISC Indication or S Channel Change A change in the layer 1 indication code or multiframe S channel has been detected. The actual value can be ...
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D_ch Receive Status Register Value after reset: 20H RDOV CRCE RMB RDOV Receive Data Overflow A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The ...
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This register contains the first choice of the first byte address of received frame. For LAPD frame, SA17 - SA12 is the SAPI value, SA11 is C/R bit and SA10 is zero. 8.1.14 D_ch SAPI2 Register D_SAP2 Value after reset: ...
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TA27 TA26 TA25 TA24 TA27 - TA20 This register contains the second choice of the second byte address of received frame. For LAPD frame, TA27 - TA21 is the TEI value, TA20 8.1.18 D_ch Receive Frame ...
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TMD Timer 2 Mode 0: One shot count down mode. The timer starts when it is written a non-zero count value and stops when it reaches zero. 1: Cyclic timer mode. The timer starts when it is written a non-zero ...
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Note: When SRST = 1, the chip is in reset state. Read or write to any of the registers except SRST bit is inhibited at this time. OPS1-0 Output Phase Delay Compensation Select1-0 These two bits select the output phase ...
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CODX3-0 Layer 1 Command Code Value of the command code transmitted to layer 1. A read to this register returns the previous written value. Note: If S/T layer 1 function is disabled and GCI slave mode is ...
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SCIE SCIE S Channel Change Interrupt Enable This bit is used to enable/disable the generation of CIR:SCC status bit and interrupt Status bit and interrupt are disabled Status bit and ...
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OE0 Direction Control for IO1-0 Used when XMODE=0 only Pin IO1-0's output drivers are disabled Pin IO1-0's output drivers are enabled. PXC PCM Cross-connect This bit determines whether or not the PCM ports are cross-connected with ...
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MDR0 Monitor channel 0 Data Receive MER0 Monitor channel 0 End of Reception MDA0 Monitor channel 0 Data Acknowledged The remote end has acknowledged the Monitor byte being transmitted. MAB0 Monitor channel 0 Data Abort 8.1.31 Monitor Channel 0 Control ...
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MAC1 Monitor Transmit Channel 1 Active (Read Only) Data transmission is in progress in GCI mode Monitor channel 1. 0: the previous transmission has been terminated. Before starting a transmission, the microprocessor should verify that the transmitter is inactive. 1: ...
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IO7 IO6 IO5 IO4 IO1-0 Read or Write Data of Pins IO1-0 On read operation, these are the present values of pins IO1-0. On write operation, the data are driven to pins IO1-0 only if PCTL:OE0=1. IO3-2 ...
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Contains the Monitor channel data received in GCI Monitor channel 1 according to the Monitor channel protocol. 8.1.36 Monitor Transmit Channel 1 Register Value after reset: FFH Contains the Monitor channel data transmitted in GCI Monitor channel ...
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MXIE1 Monitor channel 1 Transmit Interrupt Enable Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0). MXC1 MX bit Control Determines the value of the MX bit always internally controlled by the ...
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Bit 7-0 Transmit data of GCI IC2 channel. A read to this register returns the previously written value. 8.1.43 GCI CI1 Indication Register Value after reset : Undefined CI1R_6 CI1R_5 CI1R_6-1 Input data of ...
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IC2 IC2 Synchronous Transfer Interrupt When enabled, an interrupt is generated at end of GCI IC2 time slot every GCI frame (125 s). CI1 GCI CI1 Synchronous Transfer Interrupt When enabled, an interrupt is generated when there is a change ...
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TABLE 8.4 REGISTER SUMMARY: B1 CHANNEL HDLC Offset R/W Name B1_RFIFO 21 W B1_XFIFO 22 R/W B1_CMDR RACK 23 R/W B1_MODE MMS 24 R_clr B1_EXIR 25 R/W B1_EXIM 26 R B1_STAR 27 R/W B1_ADM1 MA17 28 R/W ...
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When the number of empty locations is equal to or greater than the threshold value, a XFR interrupt is generated. After a XFR interrupt bytes of data can be written into this FIFO for transmission. ...
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XME Transmit Message End In transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch HDLC controller transmits the data in FIFO and automatically appends the CRC and the closing flag sequence in transparent mode. ...
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The data rate in B1 channel is 64 kbps. 1: The data rate in B1 channel is 56 kbps. The most significant bit in each octet is fixed at "1". Note kbps mode, only transparent mode can ...
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B1_ch Extended Interrupt Mask Register B1_EXIM Value after reset: FFH RMR RME RDOV Setting the bit to "1" masks the corresponding interrupt source in B1_EXIR register. Masked interrupt status bits are read as zero when ...
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B1_ch Address Mask Register 1 Value after reset: 00H MA17 MA16 MA15 MA14 MA17-10 Address Mask Bits Used in transparent mode only. These bits mask the first byte address comparisons. If the mask bit is ...
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RA27 RA26 RA25 RA24 RA27-20 Address Bits Used in transparent mode only. These bits are used for the second byte address comparisons. 8.2.12 B1_ch Receive Frame Byte Count Low Value after reset: 00H RBC7 RBC6 RBC5 ...
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IDLE7 IDLE6 IDLE5 IDLE4 IDLE7-0 This pattern is transmitted when the transmitter is active and transmit FIFO is empty. Valid in extended transparent mode only. 8.3 B2 HDLC controller TABLE 8.5 REGISTER ADDRESS MAP: B2 CHANNEL ...
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R/W B2_ADR1 RA17 3A R/W B2_ADR2 RA27 3B R B2_RBCL RBC7 3C R B2_RBCH 2E R/W B2_IDLE IDLE7 The B2 channel HDLC register's definitions and functions are the same as those of B1 channel HDLC. Please refer to section ...
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Analog power I CC supply current: activated Input leakage I LI current Output leakage I LO current Absolute value V 2. output pulse 2.10 amplitude ( SX2 SX1 Transmitter I 7.5 X output current ...
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Note: The load capacitance C depends on the crystal specification. The typical values are pF. L External ocsillator input (XTAL1) clock characteristics Parameter Min. Max. Duty cycle 1:2 2:1 9.4 Preliminary Switching Characteristics 9.4.1 PCM Interface Timing ...
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Parameter Parameter Descriptions ta1 PBCK pulse high ta2 PBCK pulse low ta3 Frame clock asserted from PBCK ta4 PTXD data delay from PBCK ta5 Frame clock deasserted from PBCK ta6 PTXD hold time from PBCK ta7 PRXD setup time to ...
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Intel mode write cycle timing t1 ALE t2 t3 A<7:0> AD<7:0> t6 CS# t4 WR# Motorola mode read cycle timing A<7:0> t16 CS# t18 t20 DS# t22 RW t23 D<7:0> Motorola mode write cycle timing A<7:0> t16 CS# t18 t26 ...
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Parameter Parameter Descriptions t1 ALE pulse width t2 address setup time to ALE t3 address hold time from ALE t4 address setup time to RD#, WR# t5 RD# pulse width t6 CS# setup time to RD#, WR# t7 CS# hold ...
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... ORDERING INFORMATION Part Number Package Type W66910CD 100 Pin LQFP W66910 PCI ISDN S/T-Controller Production Flow 0 0 Commercial +70 C -79 - Publication Release Date: Data Sheet Feb,2001 Revision 1.0 ...
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PACKAGE SPECIFICATIONS 100PIN LQFP(14x20x1.4mm footprint 2.0mm) Seating Plane See Detail F y Controlling dimension : Millimeters Controlling dimension : Millimeters Dimension in inch Symbol Min Nom Max Min ...
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... Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Rm. 803, World Trade Square, Tower II Science-Based Industrial Park 123 Hoi Bun Rd., Kwun Tong Hsinchu, Taiwan Kowloon, Hong Kong TEL: 886-35-770066 TEL: 852-27516023-7 FAX: 886-35-789467 FAX: 852-27552064 www: http://www.winbond.com.tw/ Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. ...