CY7B933-SXI Cypress Semiconductor Corp, CY7B933-SXI Datasheet - Page 16

• Manufacturer Part Number: CY7B933-SXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7B933-SXI

• Lead Free Status / Rohs Status: Compliant

BIST mode is intended to check the entire function of the trans-
mitter (except the transmitter input pins and the bypass function
in the Encoder), the serial link, and the receiver. It augments
normal factory ATE testing and provides the designer with a
rigorous test mechanism to check the link transmission system
without requiring any significant system overhead.
While in bypass mode, the BIST logic will function in the same
way as in the encoded mode. MODE = HIGH and
BISTEN = LOW causes the transmitter to switch to encoded
mode and begin sending the BIST pattern, as if MODE = LOW.
When BISTEN returns to HIGH, the Transmitter resumes normal
Bypass operation. In Test mode the BIST function works as in
the Normal mode. For more information on BIST, consult the
“HOTLink Built-In Self-Test” application note.
Test Mode
The MODE input pin selects between three transmitter functional
modes. When wired to V
and load directly from the input register into the shifter. When
wired to GND, the inputs D
using the Fibre Channel 8B/10B codes and sequences (shown
at the end of this datasheet). Since the transmitter is usually
hardwired to encoded or bypass mode and not switched
between them, a third function is provided for the MODE pin. The
test mode is selected by floating the MODE pin (internal resistors
hold the MODE pin at V
incoming device tests.
The test mode causes the transmitter to function in its encoded
mode, but with OutA+/OutB+ (used as a differential test clock
input) as the bit rate clock input instead of the internal
PLL-generated bit clock. In this mode, inputs are clocked by
CKW and transfers between the Input register and Shifter are
timed by the internal counters. The bit-clock and CKW must
maintain a fixed phase and divide-by-ten ratio. The phase and
pulse width of RP are controlled by phases of the bit counter (PLL
feedback counter) as in normal mode. Input and output patterns
can be synchronized with internal logic by observing the state of
RP or the device can be initialized to match an ATE test pattern
using the following technique:
Test mode is intended to allow logical, DC, and AC testing of the
transmitter without requiring that the tester check output data
patterns at the bit rate, or accommodate the PLL lock, tracking,
and frequency range characteristics that are required when the
HOTLink part operates in its normal mode. To use OutA+/OutB+
as the test clock input, the FOTO input is held HIGH while in Test
mode. This forces the two outputs to go to a ‘PECL LOW’ which
can be ignored while the test system creates a differential input
signal at some higher voltage.
Document #: 38-02017 Rev. *H
1. With the MODE pin either HIGH or LOW, stop CKW and
2. Force the MODE pin to MID (open or V
3. Start the bit-clock and let it run for at least two cycles.
4. Start the CKW clock at the bit-clock/10 rate.
bit-clock.
are stopped.
CC
CC
/2). Test mode is used for factory or
, the D(
0–7
, SVS, and SC/D are encoded
a–j
) inputs bypass the encoder
CC
/2) while the clocks
CY7B933 HOTLink Receiver Operating Mode
Description
In normal user operation, the receiver can operate in either of
two modes. The encoded mode allows a user system to send
and receive eight-bit data and control information without first
converting it to transmission characters. The bypass mode is
used for systems in which the encoding and decoding is
performed by an external protocol controller.
In either mode, serial data is received at one of the differential
line receiver inputs and routed to the shifter and the clock
synchronization. The PLL in the clock synchronizer aligns the
internally generated bit rate clock with the incoming data stream
and clocks the data into the shifter. At the end of a byte time (ten
bit times), the data accumulated in the shifter is transferred to the
decode register.
To properly align the incoming bit stream to the intended byte
boundaries, the bit counter in the clock synchronizer must be
initialized. The framer logic block checks the incoming bit stream
for the unique pattern that defines the byte boundaries. This
combinatorial logic filter looks for the X3.230 symbol defined as
‘Special Character Comma’ (K28.5). After K28.5 is found, the
free running bit counter in the clock synchronizer block is
synchronously reset to its initial state, thus ‘framing’ the data to
the correct byte boundaries.
Since noise-induced errors can cause the incoming data to be
corrupted, and because many combinations of error and legal
data can create an alias K28.5, an option is included to disable
resynchronization of the bit counter. The framer will be inhibited
when the RF input is held LOW. When RF rises, RDY will be
inhibited until a K28.5 has been detected, and RDY will resume
its normal function. Data will continue to flow through the
Receiver while RDY is inhibited.
Encoded Mode Operation
In encoded mode the serial input data is decoded into eight bits
of data (Q
diagnostic output bit (RVS). If the pattern in the decode register
is found in the Valid Data Characters table, the context of the data
is decoded as normal message data and the SC/D output will be
LOW. If the incoming bit pattern is found in the Valid Special
Character Codes and Sequences table, it is interpreted as
‘control’ or ‘protocol information’, and the SC/D output will be
HIGH. Special characters include all protocol characters defined
for use in packets for Fibre Channel, ESCON, and other propri-
etary and diagnostic purposes.
The violation symbol that can be explicitly sent as part of a user
data packet (that is, transmitter sending C0.7; D
and SC/D = 1; or SVS = 1) will be decoded and indicated in
exactly the same way as a noise-induced error in the trans-
mission link. This function will allow system diagnostics to
evaluate the error in an unambiguous manner, and will not
require any modification to the receiver data interface for
error-testing purposes.
0
–Q
7
), a context control bit (SC/D), and a system
CY7B923, CY7B933
7–0
Page 16 of 40
= 111 00000
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