MT46H16M32LFCM-6 IT:B Micron Technology Inc, MT46H16M32LFCM-6 IT:B Datasheet - Page 57

• Manufacturer Part Number: MT46H16M32LFCM-6 IT:B
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCM-6 IT:B

• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Status Read Register
Figure 21: Status Read Register Timing
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Command
BA0, BA1
Address
DQS
CK#
DQ
CK
PRE
T0
1
Notes:
t
NOP
RP
T1
The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh
multiplier, width type, and density of the device, as shown in Figure 22 (page 58). The
SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0. The
sequence to perform an SRR command is as follows:
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first
bit of the burst, with the output being “Don’t Care” on the second bit of the burst.
1. The device must be properly initialized and in the idle or all banks precharged state.
2. Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins
3. Wait
4. Issue a READ command.
5. Subsequent commands to the device must be issued
1. All banks must be idle prior to status register read.
2. NOP or DESELECT commands are required between the LMR and READ commands
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.
5. The second bit of the data-out burst is a “Don’t Care.”
set to 0.
mand is issued; only NOP or DESELECT commands are supported during
(
as an example only.
t
SRR), and between the READ and the next VALID command (
BA0 = 1
BA1 = 0
LMR
t
0
SRR; only NOP or DESELECT commands are supported during the
T2
t
NOP
SRR
T3
2
57
READ
T4
512Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
T5
CL = 3
3
t
SRC
NOP
T6
Don’t Care
t
SRC after the SRR READ com-
Status Read Register
© 2004 Micron Technology, Inc. All rights reserved.
t
SRC).
NOP
out
SRR
4
Transitioning Data
Note 5
t
SRR time.
t
SRC.
Valid
T8