MAX5102BEUE+T Maxim Integrated Products, MAX5102BEUE+T Datasheet - Page 6

• Manufacturer Part Number: MAX5102BEUE+T
• Description: IC DAC 8BIT DUAL PAR-IN 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5102BEUE+T

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

The MAX5102 uses a matrix decoding architecture for the
DACs. The external reference voltage is divided down by
a resistor string placed in a matrix fashion. Row and col-
umn decoders select the appropriate tab from the resistor
string to provide the needed analog voltages. The resistor
network converts the 8-bit digital input into an equivalent
analog output voltage in proportion to the applied refer-
ence voltage input. The resistor string presents a code-
independent input impedance to the reference and
guarantees a monotonic output.
These devices can be used in multiplying applications.
Their voltages are buffered by rail-to-rail op amps con-
nected in a follower configuration to provide a rail-to-rail
output (see Functional Diagram).
The MAX5102 features a shutdown mode that reduces
current consumption to 1nA. A high voltage on the
SHDN pin shuts down the DACs and the output ampli-
fiers. In shutdown mode, the output amplifiers enter a
high-impedance state. When bringing the device out of
shutdown, allow 13µs for the output to stabilize.
The DAC outputs are internally buffered by precision
amplifiers with a typical slew rate of 0.6V/µs. The typical
settling time to ±1/2LSB at the output is 6µs when
loaded with 10kΩ in parallel with 100pF.
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
6
5–12
PIN
13
14
15
16
_______________________________________________________________________________________
1
2
3
4
D7–D0
NAME
SHDN
OUTB
OUTA
GND
V
REF
WR
A0
DD
Low-Power Shutdown Mode
Positive Supply Voltage. Bypass V
Reference Voltage Input
Shutdown. Connect SHDN to GND for normal operation.
Write Input (active low). Use WR to load data into the DAC input latch selected by A0.
Data Inputs
DAC Address Select Bit
Ground
DAC B Voltage Output
DAC A Voltage Output
Detailed Description
Digital-to-Analog Section
Output Buffer Amplifiers
DD
to GND using a 0.1µF capacitor.
The MAX5102 provides a code-independent input
impedance on the REF input. Input impedance is typi-
cally 460kΩ in parallel with 15pF, and the reference
input voltage range is 0 to V
accepts positive DC signals, as well as AC signals with
peak values between 0 and V
sets the full-scale output voltage for the DAC. The out-
put voltage (V
digitally programmable voltage source as follows:
where N
code.
In the MAX5102, address line A0 selects the DAC that
receives data from D0–D7, as shown in Table 1. When
WR is low, the addressed DAC’s input latch is transpar-
ent. Data is latched when WR is high. The DAC outputs
(OUTA, OUTB) represent the data held in the two 8-bit
Table 1. MAX5102 Addressing Table
(partial list)
H = High state, L = Low state, X = Don’t care
FUNCTION
WR
H
L
L
B
is the numeric value of the DAC binary input
Digital Inputs and Interface Logic
OUT
V
OUT
A0
H
X
L
) for any DAC is represented by a
= (N
Input data latched
DAC A input latch transparent
DAC B input latch transparent
B
· V
REF
DD
Pin Description
DD
. The reference input
LATCH STATE
) / 256
. The voltage at REF
Reference Input