CY7C4245-15JC Cypress Semiconductor Corp, CY7C4245-15JC Datasheet - Page 10

• Manufacturer Part Number: CY7C4245-15JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4245-15JC

• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 4Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Programmable Almost Empty Flag Timing
Notes:
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
19. PAE offset – n. Number of data words into FIFO already = n.
20. PAE offset – n.
21. t
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
PAE
WEN
WEN2
rising RCLK is less than t
WCLK
WCLK
SKEW3
RCLK
RCLK
WEN
REN
PAE
REN
]
[19]
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
t
CLKH
SKEW3
, then PAE may not change state until the next RCLK.
(continued)
t
SKEW3
t
CLKH
t
t
ENS
ENS
[21]
t
t
ENH
ENH
t
CLKL
Note
20
t
ENS
10
t
ENH
t
PAEsynch
t
CLKL
t
PAE
t
t
ENS
ENS
n+1 WORDS
N + 1 WORDS
IN FIFO
INFIFO
t
ENS
t
PAE
CY7C4425/4205/4215
CY7C4225/4235/4245
t
ENH
n WORDS IN FIFO
Note
22
t
PAEsynch
42X5–14
42X5–13