MAX534AEEE Maxim Integrated Products, MAX534AEEE Datasheet - Page 4

• Manufacturer Part Number: MAX534AEEE
• Description: IC DAC QUAD +5V 8BIT R/R 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX534AEEE

• Settling Time: 8µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 667mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS (continued)
(V
Typical values are at V
+5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
4
Note 1: INL and DNL are measured with R
Note 2: V
Note 3: V
Note 4: Guaranteed by design, not production tested.
Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of V
Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other
Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for t
Note 8: When DOUT is not used. If DOUT is used, f
Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V
SERIAL-INTERFACE TIMING
SCLK Clock Frequency (Note 8)
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup
Time
SCLK Rise to CS Rise Hold Time
DIN to SCLK Rise to Setup Time
DIN to SCLK Rise to Hold Time
SCLK Rise to DOUT Valid
Propagation Delay (Note 9)
SCLK Fall to DOUT Valid
Propagation Delay (Note 10)
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Setup
Time
DD
_______________________________________________________________________________________
= +4.5V to +5.5V, V
PARAMETER
or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section.
DAC’s codes to 00 hex.
DAC.
REF
REF
= 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all other
= 4Vp-p, 10kHz. DAC code = 00 hex.
DD
REF
= +5V and T
= 4.096V, AGND = DGND = 0V, C
SYMBOL
t
t
t
f
t
t
t
A
t
CSH
t
t
DO1
DO2
CLK
t
CSS
CS0
CS1
CH
DH
CL
DS
= +25°C.)
L
referenced to ground. Nonlinearity is measured from the first code that is greater than
MAX534M
MAX534M
MAX534M
MAX534M
MAX534M
MAX534M
MAX534M
MAX534M
MAX534M
MAX534C/E
MAX534C/E
MAX534C/E
MAX534C/E
MAX534C/E
MAX534C/E
MAX534C/E
MAX534C/E
MAX534C/E
CLK
max is 4MHz, due to the SCLK to DOUT propagation delay.
CONDITIONS
DOUT
= 100pF, T
LDAC
A
or longer after CS goes high.
= T
MIN
to T
MAX
, unless otherwise noted.
MIN
40
50
40
50
40
50
40
50
40
50
40
50
0
0
OUT
’s final value.
TYP
DD
DD
MAX
200
230
210
250
8.3
).
10
).
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns