ISPLSI2064VE-200LT100 Lattice, ISPLSI2064VE-200LT100 Datasheet - Page 8

• Manufacturer Part Number: ISPLSI2064VE-200LT100
• Description: LATISPLSI2064VE-200LT100 64MC 2K Gates
• Manufacturer: Lattice

Note: Calculations are based on timing specifications for the ispLSI 2064VE-200L.
Derivations of
ispLSI 2064VE Timing Model
GOE 0,1
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
3.1ns
2.9ns
8.4ns
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
#21
#20
t
su,
I/O Cell
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (1.8) - (0.5 + 0.6 + 2.9)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (1.5 + 1.5)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
orp +
XOR Delays
#33, 34,
Control
PTs
t
#25, 26, 27
Feedback
grp +
t
20 PT
35
grp +
#24
Comb 4 PT Bypass #23
8
t
ob)
t
OE
RE
CK
ptck(min))
t
Specifications ispLSI 2064VE
20ptxor)
GLB
GLB Reg Bypass
D
RST
Table 2-0042/2064VE
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2064
#38,
39
I/O Cell
(Output)
I/O Pin