EPM2210F256C4 Altera, EPM2210F256C4 Datasheet - Page 16

• Manufacturer Part Number: EPM2210F256C4
• Description: IC MAX II CPLD 2210 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210F256C4

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 204
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Family Name: MAX II
• # Macrocells: 1700
• Frequency (max): 2.3148GHz
• Propagation Delay Time: 9.1ns
• Number Of Logic Blocks/elements: 221
• # I/os (max): 204
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1340; EPM2210F256C4

2–8
LUT Chain and Register Chain
addnsub Signal
LE Operating Modes
MAX II Device Handbook
In addition to the three general routing outputs, the LEs within an LAB have LUT
chain and register chain outputs. LUT chain connections allow LUTs within the same
LAB to cascade together for wide input functions. Register chain outputs allow
registers within the same LAB to cascade together. The register chain output allows an
LAB to use LUTs for a single combinational function and the registers to be used for
an unrelated shift register implementation. These resources speed up connections
between LABs while saving local interconnect resources. Refer to
Interconnect” on page 2–12
connections.
The LE’s dynamic adder/subtractor feature saves logic resources by using one set of
LEs to implement both an adder and a subtractor. This feature is controlled by the
LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either
A + B or A – B. The LUT computes addition; subtraction is computed by adding the
two’s complement of the intended subtractor. The LAB-wide signal converts to two’s
complement by inverting the B bits within the LAB and setting carry-in to 1, which
adds one to the least significant bit (LSB). The LSB of an adder/subtractor must be
placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically
sets the carry-in to 1. The Quartus II Compiler automatically places and uses the
adder/subtractor feature when using adder/subtractor parameterized functions.
The MAX II LE can operate in one of the following modes:
■
■
Each mode uses LE resources differently. In each mode, eight available inputs to the
LE, the four data inputs from the LAB local interconnect, carry-in0 and carry-
in1 from the previous LE, the LAB carry-in from the previous carry-chain LAB, and
the register chain connection are directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous clear,
asynchronous preset/load, synchronous clear, synchronous load, and clock enable
control for the register. These LAB-wide signals are available in all LE modes. The
addnsub control signal is allowed in arithmetic mode.
The Quartus II software, in conjunction with parameterized functions such as library
of parameterized modules (LPM) functions, automatically chooses the appropriate
mode for common functions such as counters, adders, subtractors, and arithmetic
functions.
“Normal Mode”
“Dynamic Arithmetic Mode”
for more information about LUT chain and register chain
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
“MultiTrack
Logic Elements