EPM3512AFI256-10 Altera, EPM3512AFI256-10 Datasheet - Page 5

IC MAX 3000A CPLD 512 256-FBGA

EPM3512AFI256-10

Manufacturer Part Number
EPM3512AFI256-10
Description
IC MAX 3000A CPLD 512 256-FBGA
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet

Specifications of EPM3512AFI256-10

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
208
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1993
EPM3512AFI256-10

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Figure 1. MAX 3000A Device Block Diagram
Note:
(1)
Altera Corporation
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
INPUT/OE2/GCLK2
INPUT/GCLK1
INPUT/GCLRn
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
6 or 10 Output Enables (1)
Control
Control
Block
Block
I/O
I/O
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown
in
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
6 or 10
6 or 10
Figure
2 to
16
2 to
16
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
LAB A
LAB C
1. Multiple LABs are linked together via the PIA, a global bus
Macrocells
Macrocells
33 to 48
1 to 16
MAX 3000A Programmable Logic Device Family Data Sheet
2 to 16
2 to 16
16
16
36
36
PIA
36
36
2 to 16
2 to 16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 or 10 Output Enables (1)
2 to
16
2 to
16
Control
Control
Block
Block
I/O
I/O
6 or 10
6 or 10
2 to 16 I/O
2 to 16 I/O
5

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