ATF1504AS-10JI44 Atmel, ATF1504AS-10JI44 Datasheet - Page 16

• Manufacturer Part Number: ATF1504AS-10JI44
• Description: IC CPLD 10NS 44PLCC
• Manufacturer: Atmel
• Series: ATF1504AS(L)r

Specifications of ATF1504AS-10JI44

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Macrocells: 64
• Number Of I /o: 32
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 5V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: ATF1504AS10JI44

JTAG-BST/ISP
Overview
JTAG Boundary-scan
Cell (BSC) Testing
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note:
16
The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option.
ATF1504AS(L)
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1504AS. The boundary-scan technique involves the inclusion of a shift-regis-
ter stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to
support boundary scan testing. The ATF1504AS does not currently include a Test Reset
(TRST) input pin because the TAP controller is automatically reset at power-up. The five
JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE
and HIGHZ. The ATF1504AS’s ISP can be fully described using JTAG’s BSDL as
described in IEEE Standard 1149.1b. This allows ATF1504AS programming to be
described and implemented using any one of the third-party development tools support-
ing this standard.
The ATF1504AS has the option of using four JTAG-standard I/O pins for boundary-scan
testing (BST) and in-system programming (ISP) purposes. The ATF1504AS is program-
mable through the four JTAG pins using the IEEE standard JTAG programming protocol
established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the
ISP interface for in-system programming. The JTAG feature is a programmable option.
If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O
pins.
The ATF1504AS contains up to 68 I/O pins and four input pins, depending on the device
type and package type selected. Each input pin and I/O pin has its own boundary-scan
cell (BSC) in order to support boundary-scan testing as described in detail by IEEE
Standard 1149.1. A typical BSC consists of three capture registers or scan registers and
up to two update registers. There are two types of BSCs, one for input or I/O pin, and
one for the macrocells. The BSCs in the device are chained together through the cap-
ture registers. Input to the capture register chain is fed in from the TDI pin while the
output is directed to the TDO pin. Capture registers are used to capture active device
data signals, to shift data in and out of the device and to load data into the update regis-
ters. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
0950N–PLD–07/02